eZ80® CPU User Manual
306
OTDM
Output to I/O and Decrement
Operation
({UU, 00h,C}) ← (HL)
B← B–1
C← C–1 HL ← HL–1
Description
The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory. The CPU next outputs this byte to the I/O address specified by the C register with the High byte of the address, ADDR[15:8], forced to 0. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The B, C, and HL registers are decremented.
Condition Bits Affected
S |
Undefined. |
Z |
Set if B–1=0; reset otherwise. |
H |
Undefined. |
P/V |
Undefined. |
N |
Set if msb of data is logical 1; reset otherwise. |
C |
Undefined. |
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
|
OTDM |
— |
X |
5 |
ED, 8B |
|
|
|
|
|
|
|
OTDM.S |
— |
1 |
6 |
52, |
ED, 8B |
|
|
|
|
|
|
OTDM.L |
— |
0 |
6 |
49, |
ED, 8B |
|
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|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
307
OTDMR
Output to I/O and Decrement
Operation
repeat {
({UU, 00h, C}) ← (HL)
B← B–1
C← C–1 HL ← HL–1
}while B ≠ 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory. The CPU next outputs this byte to the I/O address specified by the C register with the High byte of the address, ADDR[15:8], forced to 0. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The B, C, and HL registers are decremented. The instruction repeats until register B equals 0.
Condition Bits Affected
S |
Undefined. |
Z |
Set if B–1=0; reset otherwise. |
H |
Undefined. |
P/V |
Undefined. |
N |
Set if msb of data is logical 1; reset otherwise. |
C |
Undefined. |
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
|
OTDMR |
— |
X |
2 + 3 * B |
ED, 9B |
|
|
|
|
|
|
|
OTDMR.S |
— |
1 |
3 + 3 * B |
52, |
ED, 9B |
|
|
|
|
|
|
OTDMR.L |
— |
0 |
3 + 3 * B |
49, |
ED, 9B |
|
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
308
OTDR
Output to I/O and Decrement
Operation
repeat {
({UU, BC[15:0]}) ← (HL) B ← B–1
HL ← HL–1 } while B ≠ 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory. The CPU next outputs this byte to I/O address {UU, BC[15:0]}. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The B and HL registers are decremented. The instruction repeats until register B equals 0.
Condition Bits Affected
S Not affected.
Z Set if B–1=0; reset otherwise.
H Not affected.
P/V Not affected.
N Set if msb of data is logical 1; reset otherwise.
C Not affected.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
|
OTDR |
— |
X |
2 + 3 * B |
ED, BB |
|
|
|
|
|
|
|
OTDR.S |
— |
1 |
3 + 3 * B |
52, |
ED, BB |
|
|
|
|
|
|
OTDR.L |
— |
0 |
3 + 3 * B |
49, |
ED, BB |
|
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
309
OTDRX
Output to I/O and Decrement Memory Address with Stationary I/O Address
Operation
repeat {
{UU, DE[15:0]} ← (HL) BC ← BC–1
HL ← HL–1 } while BC ≠ 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory. The CPU next outputs this byte to the I/O address {UU, DE[15:0]}. The upper byte of I/O addresses is undefined. The BC and HL registers decrement. The Z Flag is set to 1 if the BC register decrements to 0. The instruction repeats until the BC register equals 0.
Condition Bits Affected
S Not affected.
Z Set of BC–1=0; reset otherwise.
H Not affected.
P/V Not affected.
N Set if msb of data is logical 1; reset otherwise.
C Not affected.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
|||
OTDRX |
— |
X |
2 |
+ 3 |
* BC ED, CB |
||
|
|
|
|
|
|
|
|
OTDRX.S |
— |
1 |
3 |
+ 3 |
* BC 52, |
ED, CB |
|
|
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|
|
|
|
|
|
OTDRX.L |
— |
0 |
3 |
+ 3 |
* BC 49, |
ED, CB |
|
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|
|
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|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
310
Note
This instruction is not supported on the eZ80190 device.
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
311
OTI2R
Output to I/O and Increment with Repeat
Operation
repeat {
({UU, DE[15:0]}) ← (HL) BC ← BC–1
DE ← DE+1
HL ← HL+1 } while BC ≠ 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory. The CPU next outputs this byte to I/O address {UU, DE[15:0]}. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The BC register decrements. The DE and HL registers increment. The instruction repeats until register BC equals 0.
Condition Bits Affected
S Not affected.
Z Set if BC–1=0; reset otherwise.
H Not affected.
P/V Not affected.
N Set if msb of data is logical 1; reset otherwise.
C Not affected.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
|
OTI2R |
— |
X |
2 + 3 * B |
ED, B4 |
|
|
|
|
|
|
|
OTI2R.S |
— |
1 |
3 + 3 * B |
52, |
ED, B4 |
|
|
|
|
|
|
OTI2R.L |
— |
0 |
3 + 3 * B |
49, |
ED, B4 |
|
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
312
Note
This instruction operates differently in the eZ80190 device product. In the eZ80190, operation is:
repeat {
({UU, BC[15:0]}) ← (HL)
B← B–1
C← C+1 HL ← HL+1
}while B ≠ 0
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |