eZ80® CPU User Manual

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Vectored Interrupts for On-Chip Peripherals

Vectored interrupts operate in the same manner as Mode 2 interrupts, irrespective of which interrupt mode is selected. In the case of the vectored interrupts, the CPU does not fetch the low-order interrupt vector address from the data bus, D[7:0]. Instead, the CPU fetches from the internal vectored interrupt bus, at address IVECT[8:0]. The internal vectored interrupt bus is used exclusively for on-chip peripherals.

In applications that run Z80 mode code exclusively, the interrupt vector address is {MBASE, I[7:1], IVECT[8:0]}. A 16-bit word is fetched from the interrupt vector address and loaded into the lower two bytes of the Program Counter, PC[15:0].

In mixed-memory or ADL mode applications, the interrupt vector address is {I[15:1], IVECT[8:0]}. A 24-bit word is fetched from the interrupt vector address and loaded into the Program Counter, PC[23:0].

Note: The eZ80190, eZ80L92, and eZ80F92/F93 devices only support an 8-bit I register, an 8-bit IVECT, and a 16-bit word fetch in ADL modes. Refer to the eZ80 and eZ80Acclaim! product specifications for information on product specific vectored interrupt modes.

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Table 25. Vectored Interrupt Operation

	ADL	MADL
Memory Mode	Bit	Bit	Operation
Z80 Mode	0	0	Read the LSB of the interrupt vector placed on the internal
			vectored interrupt bus, IVECT [8:0], by the interrupting
			peripheral.
			• IEF1 ← 0
			• IEF2 ← 0
			• The starting Program Counter is effectively {MBASE,
			PC[15:0]}.
			• Push the 2-byte return address PC[15:0] onto the
			({MBASE,SPS}) stack.
			• The ADL mode bit remains cleared to 0.
			• The interrupt vector address is located at { MBASE,
			I[7:1], IVECT[8:0] }.
			• PC[15:0] ← ( { MBASE, I[7:1], IVECT[8:0] } ).
			• The ending Program Counter is effectively {MBASE,
			PC[15:0]}
			• The interrupt service routine must end with RETI.
ADL Mode	1	0	Read the LSB of the interrupt vector placed on the internal
			vectored interrupt bus, IVECT [8:0], by the interrupting
			peripheral.
			• IEF1 ← 0
			• IEF2 ← 0
			• The starting Program Counter is PC[23:0].
			• Push the 3-byte return address, PC[23:0], onto the SPL
			stack.
			• The ADL mode bit remains set to 1.
			• The interrupt vector address is located at { I[15:1],
			IVECT[8:0] }.
			• PC[23:0] ← ( { I[15:1], IVECT[8:0] } ).
			• The ending Program Counter is { PC[23:0] }.
			• The interrupt service routine must end with RETI.

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Table 25. Vectored Interrupt Operation (Continued)

	ADL	MADL
Memory Mode	Bit	Bit	Operation
Z80 Mode	0	1	Read the LSB of the interrupt vector placed on the internal
			vectored interrupt bus, IVECT[8:0], bus by the interrupting
			peripheral.
			• IEF1 ← 0
			• IEF2 ← 0
			• The starting Program Counter is effectively {MBASE,
			PC[15:0]}.
			• Push the 2-byte return address, PC[15:0], onto the SPL
			stack.
			• Push a 00h byte onto the SPL stack to indicate an interrupt
			from Z80 mode (because ADL = 0).
			• Set the ADL mode bit to 1.
			• The interrupt vector address is located at { I[15:1],
			IVECT[8:0] }.
			• PC[23:0] ← ( { I[15:1], IVECT[8:0] } ).
			• The ending Program Counter is { PC[23:0] }.
			• The interrupt service routine must end with RETI.L
ADL Mode	1	1	Read the LSB of the interrupt vector placed on the internal
			vectored interrupt bus, IVECT [8:0], by the interrupting
			peripheral.
			• IEF1 ← 0
			• IEF2 ← 0
			• The starting Program Counter is PC[23:0].
			• Push the 3-byte return address, PC[23:0], onto the SPL
			stack.
			• Push a 01h byte onto the SPL stack to indicate a restart
			from ADL mode (because ADL = 1).
			• The ADL mode bit remains set to 1.
			• The interrupt vector address is located at {I[15:1],
			IVECT[8:0]}.
			• PC[23:0] ← ( { I[15:1], IVECT[8:0] } ).
			• The ending Program Counter is { PC[23:0] }.
			• The interrupt service routine must end with RETI.L

UM007712-0503

PRELIMINARY

Interrupts