eZ80® CPU User Manual
373
RLCA
Rotate Left with Carry–Accumulator
Operation
C |
7 |
0 |
|
|
A |
Description
The CPU manipulates the contents of the accumulator, A, by rotating them left one bit position. The CPU next copies bit 7 into the Carry Flag and into bit 0.
Condition Bits Affected
S Not affected.
Z Not affected.
H Reset.
P/V Not affected.
N Reset.
C Data from bit 7 of the accumulator
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
RLCA |
— |
X |
1 |
07 |
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
374
RLD
Rotate Left Decimal
Operation
|
|
|
|
|
|
|
|
|
|
|
|
A |
7 |
4 |
3 |
0 |
|
7 |
4 |
3 |
0 |
(HL) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A[3:0] ← HL[7:4]
HL[7:4] ← HL[3:0]
HL[3:0] ←A[3:0]
Description
The CPU copies the contents of the low-order four bits of the memory location (HL) into the high-order four bits of the (HL). The CPU next copies the previous contents of the high-order four bits of the (HL) into the low-order four bits of the accumulator, A. The CPU next copies the previous contents of the low-order four bits of the accumulator into the low-order four bits of the (HL).
Condition Bits Affected
S |
Set if the accumulator is negative; reset otherwise. |
Z |
Set if the accumulator is 0; reset otherwise. |
H |
Reset. |
P/V |
Set if parity of the accumulator is even; reset otherwise. |
N |
Reset. |
C |
Not affected. |
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
375
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
RLD |
— |
X |
5 |
ED, 6F |
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
376
RR (HL)
Rotate Right
Operation
C |
7 |
0 |
(HL)
Description
The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). The CPU manipulates the contents of this memory location, (HL), by rotating them right one bit position. The CPU next copies the contents of bit 0 into the Carry Flag and copies the previous contents of the Carry Flag into bit 7 of the memory location, (HL).
Condition Bits Affected
\
S Set if result is negative; reset otherwise.
Z Set if result is 0; reset otherwise.
H Reset.
P/V Set if parity is even; reset otherwise.
N Reset.
C Data from bit 0 of the source.
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
377
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
|
RR |
(HL) |
X |
5 |
CB, 1E |
|
|
|
|
|
|
|
RR.S |
(HL) |
1 |
6 |
52, |
CB, 1E |
|
|
|
|
|
|
RR.L |
(HL) |
0 |
6 |
49, |
CB, 1E |
|
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
378
RR (IX/Y+d)
Rotate Right
Operation
C |
7 |
0 |
(IX/Y+d)
Description
The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-com- plement displacement d. The CPU manipulates the contents of this memory location, (IX/Y+d), by rotating them right one bit position. The CPU next copies the contents of bit 0 into the Carry Flag and copies the previous contents of the Carry Flag into bit 7 of the memory location, (IX/ Y+d).
Condition Bits Affected
S Set if result is negative; reset otherwise.
Z Set if result is 0; reset otherwise.
H Reset.
P/V Set if parity is even; reset otherwise.
N Reset.
C Data from bit 0 of the source.
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
379
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
RR |
(IX+d) |
X |
7 |
DD, CB, dd, 1E |
|
|
|
|
|
RR.S |
(IX+d) |
1 |
8 |
52, DD, CB, dd, 1E |
|
|
|
|
|
RR.L |
(IX+d) |
0 |
8 |
49, DD, CB, dd, 1E |
|
|
|
|
|
RR |
(IY+d) |
X |
7 |
FD, CB, dd, 1E |
|
|
|
|
|
RR.S |
(IY+d) |
1 |
8 |
52, FD, CB, dd, 1E |
|
|
|
|
|
RR.L |
(IY+d) |
0 |
8 |
49, FD, CB, dd, 1E |
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
380
RR r
Rotate Right
Operation
C |
7 |
0 |
r
Description
The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The CPU manipulates the contents of the r operand by rotating them right one bit position. The CPU next copies the contents of bit 0 into the Carry Flag and copies the previous contents of the Carry Flag into bit 7 of the r operand.
Condition Bits Affected
S Set if result is negative; reset otherwise.
Z Set if result is 0; reset otherwise.
H Reset.
P/V Set if parity is even; reset otherwise.
N Reset.
C Data from bit 0 of the source.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
RR |
r |
X |
2 |
CB, kk |
|
|
|
|
|
jj identifies the A, B, C, D, E, H, or L register and is assembled into one of the Op Codes indicated in Table 90.
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
381
Table 90. Register and jj Op Codes for RR r Instruction (hex)
Register |
jj |
|
|
A |
1F |
|
|
B |
18 |
|
|
C |
19 |
|
|
D |
1A |
|
|
E |
1B |
|
|
H |
1C |
|
|
L |
1D |
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
382
RRA
Rotate Right–Accumulator
Operation
C |
7 |
0 |
A
Description
The CPU manipulates the contents of the accumulator, A, by rotating them right one bit position. The CPU next copies the contents of bit 0 into the Carry Flag and copies the previous contents of the Carry Flag into bit 7.
Condition Bits Affected
S Not affected.
Z Not affected.
H Reset.
P/V Not affected.
N Reset.
C Data from bit 0 of the accumulator.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
RRA |
— |
X |
1 |
1F |
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
383
RRC (HL)
Rotate Right with Carry
Operation
C |
7 |
0 |
(HL)
Description
The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). The CPU manipulates the contents of this memory location, (HL), by rotating them right one bit position. The CPU next copies the contents of bit 0 into the Carry Flag and into bit 7 of the memory location, (HL).
Condition Bits Affected\
S Set if result is negative; reset otherwise.
Z Set if result is 0; reset otherwise.
H Reset.
P/V Set if parity is even; reset otherwise.
N Reset.
C Data from bit 0 of the source.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
|
RRC |
(HL) |
X |
5 |
CB, 0E |
|
|
|
|
|
|
|
RRC.S |
(HL) |
1 |
6 |
52, |
CB, 0E |
|
|
|
|
|
|
RRC.L |
(HL) |
0 |
6 |
49, |
CB, 0E |
|
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
384
RRC (IX/Y+d)
Rotate Right with Carry
Operation
C |
7 |
0 |
(IX/Y+d)
Description
The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-com- plement displacement d. The CPU manipulates the contents of this memory location, (IX/Y+d), by rotating them right one bit position. The CPU next copies bit 0 into the Carry Flag and into bit 7 of the memory location (IX/Y+d).
Condition Bits Affected
S Set if result is negative; reset otherwise.
Z Set if result is 0; reset otherwise.
H Reset.
P/V Set if parity is even; reset otherwise.
N Reset.
C Data from bit 0 of the source.
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
385
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
RRC |
(IX+d) |
X |
7 |
DD, CB, dd, 0E |
|
|
|
|
|
RRC.S |
(IX+d) |
1 |
8 |
52, DD, CB, dd, 0E |
|
|
|
|
|
RRC.L |
(IX+d) |
0 |
8 |
49, DD, CB, dd, 0E |
|
|
|
|
|
RRC |
(IY+d) |
X |
7 |
FD, CB, dd, 0E |
|
|
|
|
|
RRC.S |
(IY+d) |
1 |
8 |
52, FD, CB, dd, 0E |
|
|
|
|
|
RRC.L |
(IY+d) |
0 |
8 |
49, FD, CB, dd, 0E |
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
386
RRC r
Rotate Right with Carry
Operation
C |
7 |
0 |
r
Description
The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The CPU manipulates the contents of the r operand by rotating them right one bit position. The CPU next copies the contents of bit 0 into the Carry Flag and into bit 7 of the r operand.
Condition Bits Affected
S Set if result is negative; reset otherwise.
Z Set if result is 0; reset otherwise.
H Reset.
P/V Set if parity is even; reset otherwise.
N Reset.
C Data from bit 0 of the source.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
RRC |
r |
X |
2 |
CB, jj |
|
|
|
|
|
jj identifies the A, B, C, D, E, H, or L register and is assembled into one of the Op Codes indicated in Table 91.
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
387
Table 91. Register and jj Op Codes for RRC r Instruction (hex)
Register |
jj |
|
|
A |
0F |
|
|
B |
08 |
|
|
C |
09 |
|
|
D |
0A |
|
|
E |
0B |
|
|
H |
0C |
|
|
L |
0D |
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |