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eZ80 CPU user manual.2003.pdf

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eZ80® CPU User Manual

445

Op Code Maps

Table 106. Op Code Map—First Op Code

Legend

Lower Op Code Nibble

Upper

Op Code

Nibble

AND

Mnemonic

A,H

First Operand

Second Operand

Lower Nibble (Hex)

Upper Nibble (Hex)

INC

DEC

ADD

DEC

INC

DEC

NOP

BC,

RLCA

RRCA

(BC),A

B,n

AF,AF’

HL,BC

A,(BC)

C,n

Mmn

DJNZ

INC

DEC

ADD

DEC

INC

DEC

DE,

RLA

RRA

(DE),A

D,n

HL,DE

A,(DE)

E,n

Mmn

INC

DEC

ADD

DEC

INC

DEC

HL,

(Mmn),

DAA

HL,

CPL

NZ,d

H,n

Z,d

HL,HL

L,n

Mmn

(Mmn)

INC

DEC

ADD

DEC

INC

DEC

SP,

(Mmn),

SCF

C,d

CCF

NC,d

(HL)

(HL),n

HL,SP

A,n

Mmn

(Mmn)

.SIS

.LIS

sufﬁx

B,C

B,D

B,E

B,H

B,L

B,(HL)

B,A

C,B

sufﬁx

C,D

C,E

C,H

C,L

C,(HL)

C,A

.SIL

.LIL

D,B

D,C

sufﬁx

D,E

D,H

D,L

D,(HL)

D,A

E,B

E,C

E,D

sufﬁx

E,H

E,L

E,(HL)

E,A

H,B

H,C

H,D

H,E

H,H

H,L

H,(HL)

H,A

L,B

L,C

L,D

L,E

L,H

L,L

L,(HL)

L,A

HALT

(HL),B

(HL),C

(HL),D

(HL),E

(HL),H

(HL),L

(HL),A

A,B

A,C

A,D

A,E

A,H

A,L

A,(HL)

A,A

ADD

ADC

A,B

A,C

A,D

A,E

A,H

A,L

A,(HL)

A,A

A,B

A,C

A,D

A,E

A,H

A,L

A,(HL)

A,A

SUB

SBC

A,B

A,C

A,D

A,E

A,H

A,L

A,(HL)

A,A

A,B

A,C

A,D

A,E

A,H

A,L

A,(HL)

A,A

AND

XOR

A,B

A,C

A,D

A,E

A,H

A,L

A,(HL)

A,A

A,B

A,C

A,D

A,E

A,H

A,L

A,(HL)

A,A

A,B

A,C

A,D

A,E

A,H

A,L

A,(HL)

A,A

A,B

A,C

A,D

A,E

A,H

A,L

A,(HL)

A,A

RET

POP

CALL

PUSH

ADD

RST

RET

CALL

ADC

RST

NZ,

RET

Table 107

Mmn

A,n

00h

Mmn

A,n

08h

Mmn

RET

POP

OUT

CALL

PUSH

SUB

RST

RET

CALL

SBC

RST

NC,

EXX

Table 108

(n),A

A,n

10h

A,(n)

A,n

18h

Mmn

RET

POP

CALL

PUSH

AND

RST

RET

CALL

XOR

RST

PO,

PE,

Table 109

(SP),HL

A,n

20h

(HL)

DE,HL

A,n

28h

Mmn

RET

POP

CALL

PUSH

RST

RET

CALL

RST

Table 110

A,n

30h

SP,HL

A,n

38h

Mmn

Note: n=8-bit data; Mmn=16or 24-bit addr or data; d=8-bit two’s-complement displacement.

UM007712-0503

PRELIMINARY

Op Code Maps

eZ80® CPU User Manual

446

Table 107. Op Code Map—Second Op Code after 0CBh

Legend

Lower Nibble of 2nd Op Code

Upper		4
Nibble		4
of Second		RES	Mnemonic
Op Code	A	RES	Mnemonic
		4,H
First Operand			Second Operand

Upper Nibble (Hex)

Lower Nibble (Hex)

RLC

RRC

(HL)

SLA

SRA

(HL)

SRL

(HL)

BIT

0,B

0,C

0,D

0,E

0,H

0,L

0,(HL)

0,A

1,B

1,C

1,D

1,E

1,H

1,L

1,(HL)

1,A

BIT

2,B

2,C

2,D

2,E

2,H

2,L

2,(HL)

2,A

3,B

3,C

3,D

3,E

3,H

3,L

3,(HL)

3,A

BIT

4,B

4,C

4,D

4,E

4,H

4,L

4,(HL)

4,A

5,B

5,C

5,D

5,E

5,H

5,L

5,(HL)

5,A

BIT

6,B

6,C

6,D

6,E

6,H

6,L

6,(HL)

6,A

7,B

7,C

7,D

7,E

7,H

7,L

7,(HL)

7,A

RES

0,B

0,C

0,D

0,E

0,H

0,L

0,(HL)

0,A

1,B

1,C

1,D

1,E

1,H

1,L

1,(HL)

1,A

RES

2,B

2,C

2,D

2,E

2,H

2,L

2,(HL)

2,A

3,B

3,C

3,D

3,E

3,H

3,L

3,(HL)

3,A

RES

4,B

4,C

4,D

4,E

4,H

4,L

4,(HL)

4,A

5,B

5,C

5,D

5,E

5,H

5,L

5,(HL)

5,A

RES

6,B

6,C

6,D

6,E

6,H

6,L

6,(HL)

6,A

7,B

7,C

7,D

7,E

7,H

7,L

7,(HL)

7,A

SET

0,B

0,C

0,D

0,E

0,H

0,L

0,(HL)

0,A

1,B

1,C

1,D

1,E

1,H

1,L

1,(HL)

1,A

SET

2,B

2,C

2,D

2,E

2,H

2,L

2,(HL)

2,A

3,B

3,C

3,D

3,E

3,H

3,L

3,(HL)

3,A

SET

4,B

4,C

4,D

4,E

4,H

4,L

4,(HL)

4,A

5,B

5,C

5,D

5,E

5,H

5,L

5,(HL)

5,A

SET

6,B

6,C

6,D

6,E

6,H

6,L

6,(HL)

6,A

7,B

7,C

7,D

7,E

7,H

7,L

7,(HL)

7,A

Note: n=8-bit data; Mmn=16or 24-bit addr or data; d=8-bit two’s-complement displacement.

UM007712-0503

PRELIMINARY

Op Code Maps

eZ80® CPU User Manual

447

Table 108. Op Code Map—Second Op Code After 0DDh

Legend

Lower Nibble of 2nd Op Code

Upper		9
Nibble		9
Nibble
of Second		LD	Mnemonic
Op Code	F	LD	Mnemonic
Op Code	F	SP,IX
First Operand			Second Operand

Upper Nibble (Hex)

Lower Nibble (Hex)

LD BC,

ADD

(IX+d),

(IX+d)

IX,BC

LD DE,

ADD

(IX+d),

(IX+d)

IX,DE

INC

DEC

LD HL,

ADD

DEC

INC

DEC

IX,

(Mmn),

IX,

(IX+d),

IXH

IXH,n

(IX+d)

IX,IX

IXL

IXL,n

Mmn

(Mmn)

LD IY,

INC

DEC

LD (IX

LD IX,

ADD

(IX+d),

(IX+d)

+d),n

(IX+d)

IX,SP

LD B,

LD C,

B,IXH

B,IXL

(IX+d)

C,IXH

C,IXL

(IX+d)

LD D,

LD E,

D,IXH

D,IXL

(IX+d)

E,IXH

E,IXL

(IX+d)

LD H,

LD L,

IXH,B

IXH,C

IXH,D

IXH,E

IXH,IXH

IXH,IXL

(IX+d)

IXH,A

IXL,B

IXL,C

IXL,D

IXL,E

IXL,IXH

IXL,IXL

(IX+d)

IXL,A

LD A,

(IX+d),B

(IX+d),C

(IX+d),D

(IX+d),E

(IX+d),H

(IX+d),L

(IX+d),A

A,IXH

A,IXL

(IX+d)

ADD

ADD A,

ADC

ADC A,

A,IXH

A,IXL

(IX+d)

A,IXH

A,IXL

(IX+d)

SUB

SUB A,

SBC

SBC A,

A,IXH

A,IXL

(IX+d)

A,IXH

A,IXL

(IX+d)

AND

AND A,

XOR

XOR A,

A,IXH

A,IXL

(IX+d)

A,IXH

A,IXL

(IX+d)

OR A,

CP A,IXL

CP A,

A,IXH

A,IXL

(IX+d)

A,IXH

(IX+d)

Table 111

POP

PUSH

(SP),IX

(IX)

SP,IX

Note: n=8-bit datA; Mmn=16or 24-bit addr or data; d=8-bit two’s-complement displacement.

UM007712-0503

PRELIMINARY

Op Code Maps

eZ80® CPU User Manual

448

Table 109. Op Code Map—Second Op Code After 0EDh

Legend	Lower Nibble of 2nd Op Code
	Lower Nibble of 2nd Op Code
Upper

		2
Nibble		2
Nibble
of Second		SBC	Mnemonic
Op Code	4	SBC	Mnemonic
Op Code	4	HL,BC

First Operand	Second Operand

Lower Nibble (Hex)

Upper Nibble (Hex)

IN0

OUT0

LEA BC

TST

LD BC,

IN0

OUT0

TST

LD (HL),

B,(n)

(n),B

,IX+d

,IY+d

A,B

(HL)

C,(n)

(n),C

A,C

IN0

OUT0

LEA DE

TST

LD DE,

IN0

OUT0

TST

LD(HL),

D,(n)

(n),D

,IX+d

,IY+d

A,D

(HL)

E,(n)

(n),E

A,E

IN0

OUT0

LEA HL

TST

LD HL,

IN0

OUT0

TST

LD (HL),

H,(n)

(n),H

,IX+d

,IY+d

A,H

(HL)

L,(n)

(n),L

A,L

LD IY,

LEA IX

LEA IY

TST

LD IX,

IN0

OUT0

TST

LD (HL),

(HL)

,IX+d

,IY+d

A,(HL)

(HL)

A,(n)

(n),A

A,A

(HL),IY

OUT

SBC

OUT

ADC

MLT

(Mmn),

NEG

RETN

IM 0

BC,

RETI

B,(BC)

(BC),B

HL,BC

I,A

C,(BC)

(BC),C

HL,BC

R,A

(Mmn)

OUT

SBC

LEA IX

LEA IY

OUT

ADC

MLT

(Mmn),

IM 1

DE,

IM 2

D,(BC)

(BC),D

HL,DE

,IY+d

,IX+d

A,I

E,(BC)

(BC),E

HL,DE

(Mmn)

A,R

OUT

SBC

TST

PEA

OUT

ADC

MLT

(Mmn),

RRD

HL,

RLD

H,(BC)

(BC),H

HL,HL

A,n

IX+d

IY+d

L,(BC)

(BC),L

HL,HL

MB,A

A,MB

(Mmn)

SBC

TSTIO

OUT

ADC

MLT

(Mmn),

SLP

SP,

STMIX

RSMIX

HL,SP

A,(BC)

(BC),A

HL,SP

(Mmn)

INIM

OTIM

INI2

INDM

OTDM

IND2

INIMR

OTIMR

INI2R

INDMR

OTDMR

IND2R

LDI

CPI

INI

OUTI

OUTI2

LDD

CPD

IND

OUTD

OUTD2

LDIR

CPIR

INIR

OTIR

OTI2R

LDDR

CPDR

INDR

OTDR

OTD2R

INIRX

OTIRX

INDRX

OTDRX

I,HL

HL,I

Note: n=8-bit data; Mmn=16or 24-bit addr or data; d=8-bit two’s-complement displacement.

UM007712-0503

PRELIMINARY

Op Code Maps

eZ80® CPU User Manual

449

Table 110. Op Code Map—Second Op Code After 0FDh

Legend

Lower Nibble of 2nd Op Code

Upper

Nibble

of Second

Mnemonic

Op Code

SP,IY

First Operand

Second Operand

Lower Nibble (Hex)

Upper Nibble (Hex)

LD BC,

ADD

LD (IY

(IY+d)

IY,BC

+d),BC

LD DE,

ADD

LD (IY

(IY+d)

IY,DE

+d),DE

INC

DEC

LD HL,

ADD

DEC

INC

DEC

LD (IY

(Mmn),I

IY,(Mmn

IY,Mmn

IYH

IYH,n

(IY+d)

IY,IY

IYL

IYL,n

+d),HL

)

LD IX,

INC

DEC

LD (IY

LD IY,

ADD

LD (IY

(IY+d)

+d),n

(IY+d)

IY,SP

+d),IX

+d),IY

LD B,

LD C,

B,IYH

B,IYL

(IY+d)

C,IYH

C,IYL

(IY+d)

LD D,

LD E,

D,IYH

D,IYL

(IY+d)

E,IYH

E,IYL

(IY+d)

LD H,

LD L,

IYH,B

IYH,C

IYH,D

IYH,E

IYH,IYH

IYH,IYL

(IY+d)

IYH,A

IYL,B

IYL,C

IYL,D

IYL,E

IYL,IYH

IYL,IYL

(IY+d)

IYL,A

LD (IY

LD A,

+d),B

+d),C

+d),D

+d),E

+d),H

+d),L

+d),A

A,IYH

A,IYL

(IY+d)

ADD

ADD A,

ADC

ADC A,

A,IYH

A,IYL

(IY+d)

A,IYH

A,IYL

(IY+d)

SUB

SUB A,

SBC

SBC A,

A,IYH

A,IYL

(IY+d)

A,IYH

A,IYL

(IY+d)

AND

AND A,

XOR

XOR A,

A,IYH

A,IYL

(IY+d)

A,IYH

A,IYL

(IY+d)

OR A,

CP A,

A,IYH

A,IYL

(IY+d)

A,IYH

A,IYL

(IY+d)

Table 112

POP

PUSH

(SP),IY

(IY)

SP,IY

Note: n=8-bit data; Mmn=16or 24-bit addr or data; d=8-bit two’s-complement displacement.

UM007712-0503

PRELIMINARY

Op Code Maps

eZ80® CPU User Manual

450

Table 111. Op Code Map—Fourth Byte After 0DDh, 0CBh, and dd

Legend Lower Nibble of 4th Byte

Upper		6
Nibble		6
of Fourth		BIT	Mnemonic
Byte	4	BIT	Mnemonic
Byte	4	0,(IX+d)

First Operand	Second Operand

Lower Nibble (Hex)

Upper Nibble (Hex)

RLC

RRC

(IX+d)

SLA

SRA

(IX+d)

SRL

(IX+d)

BIT 0,

BIT 1,

(IX+d)

BIT 2,

BIT 3,

(IX+d)

BIT 4,

BIT 5,

(IX+d)

BIT 6,

BIT 7,

(IX+d)

RES 0,

RES 1,

(IX+d)

RES 2,

RES 3,

(IX+d)

RES 4,

RES 5,

(IX+d)

RES 6,

RES 7,

(IX+d)

SET 0,

SET 1,

(IX+d)

SET 2,

SET 3,

(IX+d)

SET 4,

SET 5,

(IX+d)

SET 6,

SET 7,

(IX+d)

Note: d=8-bit two’s-complement displacement.

UM007712-0503

PRELIMINARY

Op Code Maps

eZ80® CPU User Manual

451

Table 112. Op Code Map—Fourth Byte After 0FDh, 0CBh, and dd

Legend Lower Nibble of 4th Byte

Upper		6
Nibble		6
of Fourth		BIT	Mnemonic
Byte	4	BIT	Mnemonic
	4	0,(IY+d)
First Operand			Second Operand

Lower Nibble (Hex)

Upper Nibble (Hex)

RLC

RRC

(IY+d)

SLA

SRA

(IY+d)

SRL

(IY+d)

BIT 0,

BIT 1,

(IY+d)

BIT 2,

BIT 3,

(IY+d)

BIT 4,

BIT 5,

(IY+d)

BIT 6,

BIT 7,

(IY+d)

RES 0,

RES 1,

(IY+d)

RES 2,

RES 3,

(IY+d)

RES 4,

RES 5,

(IY+d)

RES 6,

RES 7,

(IY+d)

SET 0,

SET 1,

(IY+d)

SET 2,

SET 3,

(IY+d)

SET 4,

SET 5,

(IY+d)

SET 6,

SET 7,

(IY+d)

Note: d=8-bit two’s-complement displacement.

UM007712-0503

PRELIMINARY

Op Code Maps

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