eZ80® CPU User Manual
x
Manual Objectives
This user manual describes the architecture and instruction set of the eZ80® CPU User Manual.
About This Manual
ZiLOG recommends that the user read and understand everything in this manual before setting up and using the product. However, we recognize that there are different styles of learning. Therefore, we have designed this manual to be used either as a how to procedural manual or a reference guide to important data.
Intended Audience
This document is written for ZiLOG customers who are experienced at working with microcontrollers or in writing assembly code or compilers.
Manual Organization
The eZ80® CPU User Manual is divided into twelve sections; each section details a specific topic about the product.
Introduction
Presents an introduction to the eZ80® CPU, ZiLOG’s next-generation processor core.
Architectural Overview
Presents an overview of the eZ80® CPU’s features and benefits, and a description of the eZ80® processor.
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Memory Modes
Describes the eZ80®’s two memory modes: ADL and Z80.
Registers and Bit Flags
Offers register and bit descriptions for ADL and Z80 modes.
Memory Mode Switching
A description of switching capability between ADL and Z80 modes.
Interrupts
Describes interrupt operation in maskable and nonmaskable mixed memory modes.
Illegal Instruction Traps
Describes the consequences of undefined operations.
I/O Space
Describes input/output memory for onand off-chip peripherals.
Addressing Modes
Discusses methods of accessing different addressing modes.
Mixed-Memory Mode Applications
Discusses the MADL control bit and mixed memory mode guidelines.
CPU Instruction Set
Lists assembly language instructions, including mnemonic definitions and a summary of the eZ80® CPU instruction set.
Op Code Maps
Presents a detailed diagram of each Op Code segment.
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Manual Conventions
The following assumptions and conventions are adopted to provide clarity and ease of use:
Courier Typeface
Commands, code lines and fragments, bits, equations, hexadecimal addresses, and various executable items are distinguished from general text by the use of the Courier typeface. Where the use of the font is not indicated, as in the Index, the name of the entity is presented in upper case.
•Example: FLAGS[1] is smrf.
Hexadecimal Values
Hexadecimal values are designated by a lowercase h and appear in the Courier typeface.
•Example: STAT is set to F8h.
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Brackets
The square brackets, [ ], indicate a register or bus.
•Example: for the register REG1[7:0], REG1 is an 8-bit register, REG1[7] is the msb, and REG1[0] is the lsb.
Braces
The curly braces, { }, indicate a single register or bus created by concatenating some combination of smaller registers, or buses.
•Example: the 24-bit register {00h, REG1[7:0], REG2[7:0]} is composed of an 8-bit hexadecimal value (00h) and two 8-bit registers, REG1 and REG2. 00h is the MSB of the 24-bit register, and REG2 is the LSB of the 24-bit register.
Parentheses
The parentheses, ( ), indicate an indirect register address lookup.
•Example: (BC) is the memory location referenced by the address contained in the BC register.
Parentheses/Bracket Combinations
The parentheses, ( ), indicate an indirect register address lookup and the square brackets, [ ], indicate a register or bus.
•Example: assume BC[15:0] contains the value 1234h. ({37h, BC[15:0]}) then refers to the contents of the memory location at address 371234h.
Use of the Words Set and Clear
The words set and clear imply that a register bit or a condition contains a logical 1 and a logical 0, respectively. When either of these terms is followed by a number, the word logical may not be included; however, it is implied.
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Use of the Terms LSB and MSB
In this document, the terms LSB and MSB, when appearing in upper case, mean least significant byte and most significant byte, respectively. The lowercase forms, msb and lsb, mean least significant bit and most significant bit, respectively.
Use of Initial Uppercase Letters
Initial uppercase letters designate settings, modes, and conditions in general text.
•
•
•
Example: The Slave receiver leaves the data line High.
Example 1: The receiver forces the SCL line to Low.
The Master can generate a Stop condition to abort the transfer.
Use of All Uppercase Letters
The use of all uppercase letters designates the names of states, modes, and commands.
•Example 1: The bus is considered BUSY after the Start condition.
•Example 2: In TRANSMIT mode, the byte is sent most significant bit first.
•Example 3: A START command triggers the processing of the initialization sequence.
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