eZ80® CPU User Manual
324
OUTD
Output to I/O and Decrement
Operation
({UU, BC[15:0]}) ← (HL) B ← B–1
HL ← HL–1
Description
The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory. The CPU next outputs this byte to I/O address {UU, BC[15:0]}. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The B and HL registers decrement.
Condition Bits Affected
S Not affected.
Z Set if B–1=0; reset otherwise.
H Not affected.
P/V Not affected.
N Set if msb of data is logical 1; reset otherwise.
C Not affected.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
|
OUTD |
— |
X |
5 |
ED, AB |
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|
|
|
|
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OUTD.S |
— |
1 |
6 |
52, |
ED, AB |
|
|
|
|
|
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OUTD.L |
— |
0 |
6 |
49, |
ED, AB |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
325
OUTD2
Output to I/O and Decrement
Operation
({UU, BC[15:0]}) ← (HL)
B← B–1
C← C–1 HL ← HL–1
Description
The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory. The CPU next outputs this byte to I/O address {UU, BC[15:0]}. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The B, C, and HL registers decrement.
Condition Bits Affected
S Not affected.
Z Set if B–1=0; reset otherwise.
H Not affected.
P/V Not affected.
N Set if msb of data is logical 1; reset otherwise.
C Not affected.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
|
OUTD2 |
— |
X |
5 |
ED, AC |
|
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|
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OUTD2.S |
— |
1 |
6 |
52, |
ED, AC |
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|
|
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|
OUTD2.L |
— |
0 |
6 |
49, |
ED, AC |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
326
OUTI
Output to I/O and Increment
Operation
({UU, BC[15:0]}) ← (HL) B ← B–1
HL ← HL+1
Description
The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory. The CPU next outputs this byte to I/O address {UU, BC[15:0]}. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The B register decrements, and the HL register increments.
Condition Bits Affected
S Not affected.
Z Set if B–1=0; reset otherwise.
H Not affected.
P/V Not affected.
N Set if msb of data is logical 1; reset otherwise.
C Not affected.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
|
OUTI |
— |
X |
5 |
ED, A3 |
|
|
|
|
|
|
|
OUTI.S |
— |
1 |
6 |
52, |
ED, A3 |
|
|
|
|
|
|
OUTI.L |
— |
0 |
6 |
49, |
ED, A3 |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
327
OUTI2
Output to I/O and Increment
Operation
({UU, BC[15:0]}) ← (HL)
B← B–1
C← C+1 HL ← HL+1
Description
The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory. The CPU next outputs this byte to I/O address {UU, BC[15:0]}. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The B register decrements. The C and HL registers increment.
Condition Bits Affected
S Not affected.
Z Set if B–1=0; reset otherwise.
H Not affected.
P/V Not affected.
N Set if msb of data is logical 1; reset otherwise.
C Not affected.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
|
OUTI2 |
— |
X |
5 |
ED, A4 |
|
|
|
|
|
|
|
OUTI2.S |
— |
1 |
6 |
52, |
ED, A4 |
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|
OUTI2.L |
— |
0 |
6 |
49, |
ED, A4 |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
328
PEA IX+d
Push Effective Address
Operation
if ADL mode{
(SPL–1) ← IXd[23:16]
(SPL–2) ← IXd[15:8]
(SPL–3) ← IXd[7:0] SPL ← SPL–3
}
else Z80 mode {
(SPS–1) ← IXd[15:8]
(SPS–2) ← IXd[7:0] SPS ← SPS–2
}
where IXd indicates the sum of the contents of the register IX and the two’s- complement displacement d.
Description
In ADL mode, the 24-bit sum of the contents of IX and the two’s-comple- ment displacement d is pushed onto the stack at SPL. The stack pointer, SPL, decrements by 3.
In Z80 mode, the 16-bit sum of the contents of IX and the two’s-comple- ment displacement d is pushed onto the stack at SPS. The stack pointer, SPS, decrements by 2.
Condition Bits Affected
None.
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
329
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
||
PEA |
IX+d |
0/1 |
5/6 |
ED, 65, |
dd |
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PEA.S |
IX+d |
1 |
6 |
52, |
ED, |
65, dd |
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PEA.L |
IX+d |
0 |
7 |
49, |
ED, |
65, dd |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
330
PEA IY+d
Push Effective Address
Operation
if ADL mode{
(SPL–1) ← IYd[23:16]
(SPL–2) ← IYd[15:8]
(SPL–3) ← IYd[7:0] SPL ← SPL–3
}
else Z80 mode {
(SPS–1) ← IYd[15:8]
(SPS–2) ← IYd[7:0] SPS ← SPS–2
}
where IYd indicates the sum of the contents of the register IY and the two’s- complement displacement d.
Description
In ADL mode, the 24-bit sum of the contents of IY and the two’s-comple- ment displacement d is pushed onto the stack at SPL. The stack pointer, SPL, decrements by 3. The most significant byte (MSB) is pushed onto the stack first.
In Z80 mode, the 16-bit sum of the contents of IY and the two’s-comple- ment displacement d is pushed onto the stack at SPS. The stack pointer, SPS, decrements by 2. The most significant byte (MSB) is pushed onto the stack first.
Condition Bits Affected
None.
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
331
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
||
PEA |
IY+d |
0/1 |
5/6 |
ED, 66, |
dd |
|
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PEA.S |
IY+d |
1 |
6 |
52, |
ED, |
66, dd |
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PEA.L |
IY+d |
0 |
7 |
49, |
ED, |
66, dd |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
332
POP AF
Pop Stack
Operation
if ADL mode { F ← (SPL)
A ← (SPL+1) Discard ← (SPL+2) SPL ← SPL+3
}
else Z80 mode { F ← (SPS)
A ← (SPS+1)
SPS ← SPS+2
}
Description
In ADL mode, or when the .L suffix is employed, 3 bytes are popped off the stack beginning at the memory location specified by SPL. The first byte popped off the stack from SPL is written to the Flags Register, F. The second byte popped off the stack from (SPL+1) is written to the accumulator, A. The third byte popped off the stack from (SPL+2) is discarded. The SPL increments by 3.
In Z80 mode, or when the .S suffix is employed, 2 bytes are popped off the stack beginning at the memory location specified by SPS. The first byte popped off the stack from SPS is written to the Flags Register, F. The second byte popped off the stack from (SPS+1) is written to the accumulator, A. The SPS increments by 2.
Condition Bits Affected
The condition bits are written with the Flags register (F) value popped from the stack.
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
333
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
POP |
AF |
0/1 |
3/4 |
F1 |
|
|
|
|
|
POP.S |
AF |
1 |
4 |
52, F1 |
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|
POP.L |
AF |
0 |
5 |
49, F1 |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
334
POP IX/Y
Pop Stack
Operation
if ADL mode { IX/Y[7:0] ← (SPL)
IX/Y[15:8] ← (SPL+1) IX/Y[23:16] ← (SPL+2) SPL ← SPL+3
}
else Z80 mode { IX/Y[7:0] ← (SPS) IX/Y[15:8] ← (SPS+1) SPS ← SPS+2
}
Description
In ADL mode, or when the .L suffix is employed, 3 bytes are popped off the stack beginning at the memory location specified by SPL. The first byte popped off the stack from SPL is written to the Low byte of the specified Index Register, IXL or IYL. The second byte popped off the stack from (SPL+1) is written to the High byte of the specified Index Register, IXH or IYH. The third byte popped off the stack from (SPL+2) is written to the upper byte of the specified Index Register, IXU or IYU. The SPL increments by 3.
In Z80 mode, or when the .S suffix is employed, the first 2 bytes are popped off the stack beginning at the memory location specified by SPS. The first byte popped off the stack from (SPS+1) is written to the Low byte of the specified Index Register, IXL or IYL. The second byte popped off the stack from (SPS+2) is written to the High byte of the specified Index Register, IXH or IYH. The SPS increments by 2.
Condition Bits Affected
None.
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
335
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
POP |
IX |
0/1 |
4/5 |
DD, E1 |
|
|
|
|
|
POP.S |
IX |
1 |
5 |
52, DD, E1 |
|
|
|
|
|
POP.L |
IX |
0 |
6 |
49, DD, E1 |
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|
POP |
IY |
0/1 |
4/5 |
FD, E1 |
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POP.S |
IY |
1 |
5 |
52, FD, E1 |
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POP.L |
IY |
0 |
6 |
49, FD, E1 |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
336
POP rr
Pop Stack
Operation
if ADL mode { rr[7:0]← (SPL) rr[15:8]← (SPL+1) rr[23:16]← (SPL+2) SPL ← SPL+3
}
else Z80 mode { rr[7:0]← (SPS) rr[15:8]← (SPS+1) SPS ← SPS+2
}
Description
The rr operand is any of the multibyte CPU registers BC, DE, or HL.
In ADL mode, or when the .L suffix is employed, 3 bytes are popped off the stack beginning at the memory location specified by SPL. The first byte popped off the stack from SPL is written to the Low byte of the specified register, rr[7:0]. The second byte popped off the stack from (SPL+1) is written to the High byte of the specified register, rr[15:8]. The third byte popped off the stack from (SPL+2) is written to the upper byte of the specified register, rr[23:16]. The SPL increments by 3.
In Z80 mode, or when the .S suffix is employed, the first 2 bytes are popped off the stack beginning at the memory location specified by SPS. The first byte popped off the stack from (SPS+1) is written to the Low byte of the specified register, rr[7:0]. The second byte popped off the stack from (SPS+2) is written to the High byte of the specified register, rr[15:8]. The SPS increments by 2.
Condition Bits Affected
None.
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
337
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
POP |
rr |
0/1 |
3/4 |
kk |
|
|
|
|
|
POP.S |
rr |
1 |
4 |
52, kk |
|
|
|
|
|
POP.L |
rr |
0 |
5 |
49, kk |
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|
kk identifies either the BC, DE, or HL multibyte register and is assembled into one of the Op Codes indicated in Table 78.
Table 78. Register and kk Op Codes for POP rr Instruction (hex)
Register kk
BC C1
DE D1
HL E1
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |