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Illegal Instruction Traps

The eZ80® CPU instruction set does not cover all possible sequences of binary values. Binary values and sequences for which no operation is defined are illegal instructions. When an eZ80® processor fetches one of these illegal instructions, it performs a TRAP operation.

While not a true eZ80® instruction, a TRAP operation functions similar to an RST 00h instruction. The function of the TRAP instruction is illustrated in the following code segment:

if ADL mode (ADL=1) { (SPL) ← PC[23:0]

if MIXED MEMORY mode (MADL=1) { (SPL) ← 03h

}

PC[23:0] ← 000000h

}

else Z80 mode (ADL=0){ SPS ← PC[15:0]

if MIXED MEMORY mode (MADL=1) { (SPL) ← 02h

}

PC[15:0] ← 0000h

Effectively, PC[23:0]={MBASE, PC[15:0]}.

The current program counter is pushed onto the stack (the stack is either SPL or SPS depending upon the current memory mode). In addition, if the program code is written for MIXED MEMORY mode (MADL=1), the current memory mode information is also pushed onto the stack.

The memory mode suffixes (.SIS, .SIL, .LIS, and .LIL) do not guarantee illegal instruction traps, even when used with instructions for which they have no meaning. For example, preceding a Complement Carry Flag instruction (CCF) with an .SIS suffix of Op Code 40h is allowed. The memory mode suffixes configure the CPU to act in a particular memory

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mode and fetch a particular number of bytes from the Op Code stream, if necessary. Because the CCF instruction is not affected by the current memory mode and does not fetch any operands, there is no effect. The memory mode Op Codes do not generate traps because they do not push into secondary pages of the Op Code tables, which may contain undefined binary values.

Some products that employ the CPU can also contain a TRAP register for capturing the illegal binary value. Refer to the eZ80 and eZ80Acclaim! product specifications for more information.

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I/O Space

A separate I/O space may include both onand off-chip peripheral devices. The eZ80® CPU is capable of addressing a 64KB I/O space with 16-bit addresses. The memory and I/O space share the same 24-bit address and 8-bit data buses. However, the I/O peripherals are accessed using special I/O instructions including IN, OUT, and TSTIO. Whenever an I/O instruction is executed the upper byte of the 24-bit address bus is undefined.

Refer to the eZ80 and eZ80Acclaim! product specifications for more information on using the I/O address space and the on-chip I/O peripherals.

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Addressing Modes

The eZ80® CPU instruction set includes many different memory addressing modes. The memory address can be formed using several different methods, as outlined in the following text. The addressing modes supported are a function of each instruction.

Implied Register Addressing

Certain Op Codes automatically imply a particular register to be used during execution. Implied register instructions include many arithmetic operations that inherently reference the accumulator (A), the Index registers (IX and IY), the Stack Pointer (SPS or SPL), or the general purpose Working Registers. Examples of instructions using implied register addressing include INC A, EXX and CCF.

Restart Addressing

The eZ80® CPU features eight special single-byte restart (RST) instructions that set the Program Counter (PC) to any of eight locations within the first 256 bytes of memory. In Z80 mode, the 16-bit program counter (PC) is set to one of the following values—0000h, 0008h, 0010h, 0018h, 0020h, 0028h, 0030h, or 0038h. In Z80 mode, the MBASE register is unaffected by a RST instruction. Therefore the restart jumps to a location on the current Z80 page. In ADL mode, the 24-bit Program Counter (PC) is set to any of the following 24-bit addresses:

•000000h

•000008h

•000010h

•000018h

•000020h

•000028h

•000030h

•000038h

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Register Indirect Addressing

The memory operand address is taken from one of the multibyte BC, DE or HL registers. Register indirect addressing is illustrated in Figure 4.

BC (16or 24-Bit)

DE (16or 24-Bit)

Operand

HL (16or 24-Bit)

Memory Space

Figure 4. Register Indirect Addressing

Immediate Addressing

The memory operands immediately follows the instruction. The memory operand can be 8, 16, or 24 bits, depending on the instruction and the memory mode in use. Immediate addressing is illustrated in Figure 5.

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Op Code
		8-bit operand
nn
Op Code
nn		16-bit operand
mm
Op Code
nn
		24-bit operand
mm
MM

Figure 5. Immediate Addressing

Indexed Addressing

In this mode of addressing, a byte of data following the Op Code contains a displacement to be added to one of the IX or IY Index registers. The displacement is a two’s-complement value in the range +127 to –128.

Indexed addressing is illustrated in Figure 6.

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Op Code 1

Op Code 2

Displacement (d)

+				Operand
				Memory Space
Index Register (IX or IY)

Figure 6. Indexed Addressing

Extended Addressing

The memory operand address is specified by two or three bytes following the Op Code. Extended addressing is illustrated in Figure 7.

Op Code

nn

mm

MM

{MM, mm, nn}			Operand

Memory Space

Figure 7. Extended Addressing

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Relative Addressing

Relative addressing uses one byte of data following the Op Code to specify a displacement from the existing program to which a program jump can occur. The displacement is a two’s-complement number that is added to the address of the Op Code following the instruction. The displacement can range from +127 to –128. Relative addressing is illustrated in

Figure 8.

Op Code 1

Displacement (d)

+	Program Counter (PC)

Figure 8. Relative Addressing

I/O Addressing

I/O addressing mode is used only by the I/O instructions IN and OUT. Refer to the I/O Space section on page 63 for more information on I/O operations.

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