eZ80® CPU User Manual
317
OTIRX
Output to I/O and Increment Memory Address with Stationary I/O Address
Operation
repeat {
{UU, DE[15:0]} ← (HL) BC ← BC–1
HL ← HL+1 } while BC ≠ 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory. The CPU next loads the contents of this byte to the I/O address {UU, DE[15:0]}. The upper byte of I/ O addresses is undefined. The BC register decrements. The HL register increments. The Z Flag is set to 1 if the BC register decrements to 0. The instruction repeats until the BC register equals 0.
Condition Bits Affected
S Not affected.
Z Set of BC–1=0; reset otherwise.
H Not affected.
P/V Not affected.
N Set if msb of data is logical 1; reset otherwise.
C Not affected.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
|||
OTIRX |
— |
X |
2 |
+ 3 |
* BC ED, C3 |
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OTIRX.S |
— |
1 |
3 |
+ 3 |
* BC 52, |
ED, C3 |
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OTIRX.L |
— |
0 |
3 |
+ 3 |
* BC 49, |
ED, C3 |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
318
Note
This instruction is not supported on the eZ80190 device.
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
319
OUT (BC), r—also OUT (C), r for Z80 compatibility
Output to I/O
Operation
({UU, BC[15:0]}) ← r
Description
The r operand is any of the A, B, C, D, E, H, and L registers. The CPU outputs the contents of this byte of the specified register to the I/O address {UU, BC[15:0]}. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses.
Condition Bits Affected
None.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
OUT |
(BC),r |
X |
3 |
ED, jj |
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jj identifies the A, B, C, D, E, H, or L register and is assembled into one of the Op Codes indicated in Table 76.
Table 76. Register and jj Op Codes for OUT (BC), r and OUT (C), r
Instructions (hex)
Register |
jj |
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A |
79 |
|
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B |
41 |
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C |
49 |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
320
Table 76. Register and jj Op Codes for OUT (BC), r and OUT (C), r Instructions (hex) (Continued)
Register |
jj |
D |
51 |
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E |
59 |
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H |
61 |
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L |
69 |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
321
OUT (n), A
Output to I/O
Operation
({UU, A, n}) ←A
Description
The n operand is placed on the lower byte of the address bus, ADDR[7:0]. The CPU places the contents of the accumulator, A, onto the middle byte of the address bus, ADDR[15:8]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The CPU next outputs the contents of the accumulator to this I/O address.
Condition Bits Affected
None.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
OUT |
(n),A |
X |
3 |
D3, nn |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
322
OUT0 (n), r
Output to I/O
Operation
({UU, 00h, n}) ← r
Description
The r operand is any of A, B, C, D, E, H, or L. The n operand is placed on the lower byte of the address bus, ADDR[7:0], while the High byte of the address bus, ADDR[15:8], is forced to 0. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The CPU next outputs the contents of the r register to the I/O address {UU, 00h, n}.
Condition Bits Affected
None.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
OUT0 |
(n),r |
X |
4 |
ED, jj, nn |
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jj identifies the A, B, C, D, E, H, or L register and is assembled into one of the Op Codes indicated in Table 77.
Table 77. Register and jj Op Codes for OUT0 (n), r Instruction (hex)
Register |
jj |
A |
39 |
|
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B |
01 |
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C |
09 |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
323
Table 77. Register and jj Op Codes for OUT0 (n), r Instruction (hex)
Register |
jj |
D |
11 |
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E |
19 |
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H |
21 |
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L |
29 |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |