- •1. Pin Configurations
- •1.1 Disclaimer
- •2. Overview
- •2.1 Block Diagram
- •2.2 Pin Descriptions
- •2.2.3 Port B (PB3...PB0)
- •2.2.4 RESET
- •2.2.5 Port A (PA7...PA0)
- •3. Resources
- •4. About Code Examples
- •5. CPU Core
- •5.1 Overview
- •5.2 Architectural Overview
- •5.4 Status Register
- •5.5 General Purpose Register File
- •5.6 Stack Pointer
- •5.7 Instruction Execution Timing
- •5.8 Reset and Interrupt Handling
- •5.8.1 Interrupt Response Time
- •6. Memories
- •6.2 SRAM Data Memory
- •6.2.1 Data Memory Access Times
- •6.3 EEPROM Data Memory
- •6.3.1 EEPROM Read/Write Access
- •6.3.2 Atomic Byte Programming
- •6.3.3 Split Byte Programming
- •6.3.4 Erase
- •6.3.5 Write
- •6.3.6 Preventing EEPROM Corruption
- •6.4 I/O Memory
- •6.4.1 General Purpose I/O Registers
- •6.5 Register Description
- •7. System Clock and Clock Options
- •7.1 Clock Systems and their Distribution
- •7.2 Clock Sources
- •7.3 Default Clock Source
- •7.4 Crystal Oscillator
- •7.6 Calibrated Internal RC Oscillator
- •7.7 External Clock
- •7.8 128 kHz Internal Oscillator
- •7.9 System Clock Prescaler
- •7.9.1 Switching Time
- •7.10 Register Description
- •8. Power Management and Sleep Modes
- •8.1 Sleep Modes
- •8.2 Idle Mode
- •8.3 ADC Noise Reduction Mode
- •8.5 Standby Mode
- •8.6 Power Reduction Register
- •8.7 Minimizing Power Consumption
- •8.7.1 Analog to Digital Converter
- •8.7.2 Analog Comparator
- •8.7.4 Internal Voltage Reference
- •8.7.5 Watchdog Timer
- •8.7.6 Port Pins
- •8.8 Register Description
- •9. System Control and Reset
- •9.0.1 Resetting the AVR
- •9.0.2 Reset Sources
- •9.0.3 Power-on Reset
- •9.0.4 External Reset
- •9.0.6 Watchdog Reset
- •9.1 Internal Voltage Reference
- •9.2 Watchdog Timer
- •9.3 Timed Sequences for Changing the Configuration of the Watchdog Timer
- •9.3.1 Safety Level 1
- •9.3.2 Safety Level 2
- •9.4 Register Description
- •10. Interrupts
- •10.1 Interrupt Vectors
- •11. External Interrupts
- •11.1 Pin Change Interrupt Timing
- •11.2 Register Description
- •12. I/O Ports
- •12.1 Overview
- •12.2 Ports as General Digital I/O
- •12.2.1 Configuring the Pin
- •12.2.2 Toggling the Pin
- •12.2.3 Switching Between Input and Output
- •12.2.4 Reading the Pin Value
- •12.2.5 Digital Input Enable and Sleep Modes
- •12.2.6 Unconnected Pins
- •12.3 Alternate Port Functions
- •12.3.1 Alternate Functions of Port A
- •12.3.2 Alternate Functions of Port B
- •12.4 Register Description
- •13. 8-bit Timer/Counter0 with PWM
- •13.1 Features
- •13.2 Overview
- •13.2.1 Registers
- •13.2.2 Definitions
- •13.3 Timer/Counter Clock Sources
- •13.4 Counter Unit
- •13.5 Output Compare Unit
- •13.5.1 Force Output Compare
- •13.5.2 Compare Match Blocking by TCNT0 Write
- •13.5.3 Using the Output Compare Unit
- •13.6 Compare Match Output Unit
- •13.6.1 Compare Output Mode and Waveform Generation
- •13.7 Modes of Operation
- •13.7.1 Normal Mode
- •13.7.2 Clear Timer on Compare Match (CTC) Mode
- •13.7.3 Fast PWM Mode
- •13.7.4 Phase Correct PWM Mode
- •13.8 Timer/Counter Timing Diagrams
- •13.9 Register Description
- •14. 16-bit Timer/Counter1
- •14.1 Features
- •14.2 Overview
- •14.2.1 Registers
- •14.2.2 Definitions
- •14.2.3 Compatibility
- •14.3.1 Reusing the Temporary High Byte Register
- •14.4 Timer/Counter Clock Sources
- •14.5 Counter Unit
- •14.6 Input Capture Unit
- •14.6.1 Input Capture Trigger Source
- •14.6.2 Noise Canceler
- •14.6.3 Using the Input Capture Unit
- •14.7 Output Compare Units
- •14.7.1 Force Output Compare
- •14.7.2 Compare Match Blocking by TCNT1 Write
- •14.7.3 Using the Output Compare Unit
- •14.8 Compare Match Output Unit
- •14.8.1 Compare Output Mode and Waveform Generation
- •14.9 Modes of Operation
- •14.9.1 Normal Mode
- •14.9.2 Clear Timer on Compare Match (CTC) Mode
- •14.9.3 Fast PWM Mode
- •14.9.4 Phase Correct PWM Mode
- •14.9.5 Phase and Frequency Correct PWM Mode
- •14.10 Timer/Counter Timing Diagrams
- •14.11 Register Description
- •15. Timer/Counter Prescaler
- •15.0.1 Prescaler Reset
- •15.0.2 External Clock Source
- •15.1 Register Description
- •16.1 Features
- •16.2 Overview
- •16.3 Functional Descriptions
- •16.3.2 SPI Master Operation Example
- •16.3.3 SPI Slave Operation Example
- •16.3.5 Start Condition Detector
- •16.3.6 Clock speed considerations
- •16.4 Alternative USI Usage
- •16.4.4 Edge Triggered External Interrupt
- •16.4.5 Software Interrupt
- •16.5 Register Descriptions
- •17. Analog Comparator
- •17.1 Analog Comparator Multiplexed Input
- •17.2 Register Description
- •18. Analog to Digital Converter
- •18.1 Features
- •18.2 Overview
- •18.3 ADC Operation
- •18.4 Starting a Conversion
- •18.5 Prescaling and Conversion Timing
- •18.6 Changing Channel or Reference Selection
- •18.6.1 ADC Input Channels
- •18.6.2 ADC Voltage Reference
- •18.7 ADC Noise Canceler
- •18.7.1 Analog Input Circuitry
- •18.7.2 Analog Noise Canceling Techniques
- •18.7.3 ADC Accuracy Definitions
- •18.8 ADC Conversion Result
- •18.8.1 Single Ended Conversion
- •18.8.2 Unipolar Differential Conversion
- •18.8.3 Bipolar Differential Conversion
- •18.9 Temperature Measurement
- •18.10 Register Description
- •18.10.3.1 ADLAR = 0
- •18.10.3.2 ADLAR = 1
- •19. debugWIRE On-chip Debug System
- •19.1 Features
- •19.2 Overview
- •19.3 Physical Interface
- •19.4 Software Break Points
- •19.5 Limitations of debugWIRE
- •19.6 Register Description
- •20. Self-Programming the Flash
- •20.0.1 Performing Page Erase by SPM
- •20.0.2 Filling the Temporary Buffer (Page Loading)
- •20.0.3 Performing a Page Write
- •20.1.1 EEPROM Write Prevents Writing to SPMCSR
- •20.1.2 Reading the Fuse and Lock Bits from Software
- •20.1.3 Preventing Flash Corruption
- •20.1.4 Programming Time for Flash when Using SPM
- •20.2 Register Description
- •21. Memory Programming
- •21.1 Program And Data Memory Lock Bits
- •21.2 Fuse Bytes
- •21.2.1 Latching of Fuses
- •21.3 Signature Bytes
- •21.4 Calibration Byte
- •21.5 Page Size
- •21.6 Serial Downloading
- •21.6.1 Serial Programming Algorithm
- •21.6.2 Serial Programming Instruction set
- •21.7 High-voltage Serial Programming
- •21.8.2 Considerations for Efficient Programming
- •21.8.3 Chip Erase
- •21.8.4 Programming the Flash
- •21.8.5 Programming the EEPROM
- •21.8.6 Reading the Flash
- •21.8.7 Reading the EEPROM
- •21.8.8 Programming and Reading the Fuse and Lock Bits
- •21.8.9 Reading the Signature Bytes and Calibration Byte
- •22. Electrical Characteristics
- •22.1 Absolute Maximum Ratings*
- •22.2 Speed Grades
- •22.3 Clock Characterizations
- •22.3.1 Calibrated Internal RC Oscillator Accuracy
- •22.3.2 External Clock Drive Waveforms
- •22.3.3 External Clock Drive
- •22.4 System and Reset Characterizations
- •22.6 Serial Programming Characteristics
- •22.7 High-voltage Serial Programming Characteristics
- •23.1 Active Supply Current
- •23.2 Idle Supply Current
- •23.3 Supply Current of IO modules
- •23.3.0.1 Example 1
- •23.5 Standby Supply Current
- •23.7 Pin Driver Strength
- •23.8 Pin Threshold and Hysteresis
- •23.9 BOD Threshold and Analog Comparator Offset
- •23.10 Internal Oscillator Speed
- •23.11 Current Consumption of Peripheral Units
- •23.12 Current Consumption in Reset and Reset Pulsewidth
- •24. Register Summary
- •25. Instruction Set Summary
- •26. Ordering Information
- •26.1 ATtiny24
- •26.2 ATtiny44
- •26.3 ATtiny84
- •27. Packaging Information
- •28. Errata
- •28.1 ATtiny24
- •28.2 ATtiny44
- •28.3 ATtiny84
- •29. Datasheet Revision History
ATtiny24/44/84
7.2Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.
Table 7-1. |
Device Clocking Options Select(1) |
|
Device Clocking Option |
CKSEL3..0 |
|
|
|
|
External Clock |
0000 |
|
|
|
|
Calibrated Internal RC Oscillator 8.0 MHz |
0010 |
|
|
|
|
Watchdog Oscillator 128 kHz |
0100 |
|
|
|
|
External Low-frequency Oscillator |
0110 |
|
|
|
|
External Crystal/Ceramic Resonator |
1000-1111 |
|
|
|
|
Reserved |
|
0101, 0111, 0011,0001 |
|
|
|
Note: 1. |
For all fuses “1” means unprogrammed while “0” means programmed. |
The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the startup, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 7-2 on page 27.
Table 7-2. |
Number of Watchdog Oscillator Cycles |
|
|
|
Typ Time-out |
|
Number of Cycles |
|
|
|
|
|
4 ms |
|
512 |
|
|
|
|
|
64 ms |
|
8K (8,192) |
|
|
|
|
7.3Default Clock Source
The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is therefore the Internal RC Oscillator running at 8.0 MHz with longest startup time and an initial system clock prescaling of 8, resulting in 1.0 MHz system clock. This default setting ensures that all users can make their desired clock source setting using an InSystem or High-voltage Programmer.
7.4Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can
be configured for use as an On-chip Oscillator, as shown in Figure 7-2. Either a quartz
crystal or a ceramic resonator may be used.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capac-itance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 7-3 on page 28. For ceramic resonators, the capacitor values given by the manufacturer should be used.
27
8006E–AVR–09/06
Figure 7-2. Crystal Oscillator Connections
C2
XTAL2
C1
XTAL1
GND
The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 7-3 on page 28.
Table 7-3. |
Crystal Oscillator Operating Modes |
|
|
|
|
|
Recommended Range for Capacitors C1 and |
CKSEL3..1 |
Frequency Range (MHz) |
|
C2 for Use with Crystals (pF) |
|
|
|
|
100(1) |
0.4 - 0.9 |
|
– |
101 |
0.9 - 3.0 |
|
12 - 22 |
|
|
|
|
110 |
3.0 - 8.0 |
|
12 - 22 |
|
|
|
|
111 |
8.0 - |
|
12 - 22 |
|
|
|
|
Notes: 1. This option should not be used with crystals, only with ceramic resonators.
The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 7-4 on page 29.
28 ATtiny24/44/84
8006E–AVR–09/06
ATtiny24/44/84
Table 7-4. |
Start-up Times for the Crystal Oscillator Clock Selection |
|
|||
|
|
Start-up Time from |
Additional Delay |
|
|
|
|
Power-down and |
from Reset |
|
|
CKSEL0 |
SUT1..0 |
Power-save |
(VCC = 5.0V) |
|
Recommended Usage |
0 |
00 |
258 CK(1) |
14CK + 4.1 ms |
|
Ceramic resonator, fast |
|
rising power |
||||
|
|
|
|
|
|
|
|
|
|
|
|
0 |
01 |
258 CK(1) |
14CK + 65 ms |
|
Ceramic resonator, slowly |
|
rising power |
||||
|
|
|
|
|
|
|
|
|
|
|
|
0 |
10 |
1K CK(2) |
14CK |
|
Ceramic resonator, BOD |
|
enabled |
||||
|
|
|
|
|
|
|
|
|
|
|
|
0 |
11 |
1K CK(2) |
14CK + 4.1 ms |
|
Ceramic resonator, fast |
|
rising power |
||||
|
|
|
|
|
|
|
|
|
|
|
|
1 |
00 |
1K CK(2) |
14CK + 65 ms |
|
Ceramic resonator, slowly |
|
rising power |
||||
|
|
|
|
|
|
|
|
|
|
|
|
1 |
01 |
16K CK |
14CK |
|
Crystal Oscillator, BOD |
|
enabled |
||||
|
|
|
|
|
|
|
|
|
|
|
|
1 |
10 |
16K CK |
14CK + 4.1 ms |
|
Crystal Oscillator, fast |
|
rising power |
||||
|
|
|
|
|
|
|
|
|
|
|
|
1 |
11 |
16K CK |
14CK + 65 ms |
|
Crystal Oscillator, slowly |
|
rising power |
||||
|
|
|
|
|
|
|
|
|
|
|
|
Notes: 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.
2.These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.
7.5Low-frequency Crystal Oscillator
To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystal oscillator must be selected by setting CKSEL fuses to ‘0110’. The crystal should be connected as shown in Figure 7-2. See the 32 kHz Crystal Oscillator Application Note for details on oscillator operation and how to choose appropriate values for C1 and C2.
When this oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 7-5.
Table 7-5. |
Start-up Times for the Low Frequency Crystal Oscillator Clock Selection |
|||
|
Start-up Time from |
|
|
|
|
Power Down and Power |
Additional Delay from |
|
|
SUT1..0 |
Save |
Reset (VCC = 5.0V) |
Recommended usage |
|
00 |
1K CK(1) |
4 ms |
Fast rising power or BOD |
|
enabled |
||||
|
|
|
||
|
|
|
|
|
01 |
1K CK(1) |
64 ms |
Slowly rising power |
|
10 |
32K CK |
64 ms |
Stable frequency at start-up |
|
|
|
|
|
|
11 |
|
Reserved |
|
|
|
|
|
|
Notes: 1. These options should only be used if frequency stability at start-up is not important for the application.
29
8006E–AVR–09/06
7.6Calibrated Internal RC Oscillator
By default, the Internal RC Oscillator provides an approximate 8 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the the user. See Table 22-1 on page 182 and ”Internal Oscillator Speed” on page 206 for more details. The device is shipped with the CKDIV8 Fuse programmed. See ”System Clock Prescaler” on page 32 for more details.
This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 7-6. If selected, it will operate with no external components. During reset, hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table 22-1 on page 182.
By changing the OSCCAL register from SW, see ”Oscillator Calibration Register – OSCCAL” on page 33, it is possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is shown as User calibration in Table 22-1 on page 182.
When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section ”Calibration Byte” on page 167.
Table 7-6. Internal Calibrated RC Oscillator Operating Modes
CKSEL3..0 |
|
Nominal Frequency |
|
|
|
0010(1) |
|
8.0 MHz |
Note: 1. The device is shipped with this option selected. |
|
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in
Table 7-7 on page 30..
Table 7-7. |
Start-up Times for the Internal Calibrated RC Oscillator Clock Selection |
||
|
Start-up Time |
Additional Delay from |
|
SUT1..0 |
from Power-down |
Reset (VCC = 5.0V) |
Recommended Usage |
00 |
6 CK |
14CK |
BOD enabled |
|
|
|
|
01 |
6 CK |
14CK + 4 ms |
Fast rising power |
|
|
|
|
10(1) |
6 CK |
14CK + 64 ms |
Slowly rising power |
11 |
|
Reserved |
|
|
|
|
|
Note: 1. |
The device is shipped with this option selected. |
|
7.7External Clock
To drive the device from an external clock source, CLKI should be driven as shown in Figure 7-3 on page 31. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
30 ATtiny24/44/84
8006E–AVR–09/06
ATtiny24/44/84
Figure 7-3. External Clock Drive Configuration
EXTERNAL
CLOCK CLKI
SIGNAL
GND
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 7-8 on page 31.
Table 7-8. |
Start-up Times for the External Clock Selection |
|
|
|
Start-up Time from Power- |
Additional Delay from |
|
SUT1..0 |
down and Power-save |
Reset |
Recommended Usage |
|
|
|
|
00 |
6 CK |
14CK |
BOD enabled |
|
|
|
|
01 |
6 CK |
14CK + 4 ms |
Fast rising power |
|
|
|
|
10 |
6 CK |
14CK + 64 ms |
Slowly rising power |
|
|
|
|
11 |
|
Reserved |
|
|
|
|
|
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. See to ”System Clock Prescaler” on page 32 for details.
31
8006E–AVR–09/06