tem clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.

An external clock source can not be prescaled.

Figure 15-2. Prescaler for Timer/Counter0

clkI/O

Clear

PSR10

T0

Synchronization

clkT0

Note: 1. The synchronization logic on the input pins (T0) is shown in Figure 15-1 on page 121.

15.1Register Description

15.1.1GTCCR – General Timer/Counter Control Register

Bit		7	6	5	4	3	2	1	0
0x23 (0x43)		TSM	–	–	–	–	–	–	PSR10	GTCCR
Read/Write		R/W	R	R	R	R	R	R	R/W
Initial Value		0	0	0	0	0	0	0	0

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the Timer/Counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR10 bit is cleared by hardware, and the Timer/Counter start counting.

• Bit 0 – PSR10: Prescaler 0 Reset Timer/Counter n

When this bit is one, the Timer/Countern prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set.

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ATtiny24/44/84

16. USI – Universal Serial Interface

16.1Features

•Two-wire Synchronous Data Transfer (Master or Slave)

•Three-wire Synchronous Data Transfer (Master or Slave)

•Data Received Interrupt

•Wakeup from Idle Mode

•In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode

•Two-wire Start Condition Detector with Interrupt Capability

16.2Overview

The Universal Serial Interface (USI), provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load.

A simplified block diagram of the USI is shown in Figure 16-1 on page 123. For the actual placement of I/O pins, refer to ”Pinout ATtiny24/44/84” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the ”Register Descriptions” on page 131.

Figure 16-1. Universal Serial Interface, Block Diagram
									D Q	DO	(Output only)
									LE
										DI/SDA	(Input/Open Drain)
	Bit7							Bit0
								3
					USIDR			2
								1	TIM0 COMP
								0
								3	0		(Input/Open Drain)
								2	1	USCK/SCL
BUS	USISIF	USIOIF	USIPF	USIDC		4-bit Counter
								1
								0		CLOCK
										HOLD
DATA									[1]	Two-wire Clock
					USISR
										Control Unit
						2
	USISIE	USIOIE	USIWM1	USIWM0	USICS1	USICS0	USICLK	USITC
					USICR

The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and outgoing data. The register has no buffering so the data must be read as quickly as possible to ensure that no data is lost. The most significant bit is connected to one of two output pins depending of the wire mode configuration. A transparent latch is inserted between the Serial Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration.

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