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Рыбницкий Филиал Приднестровского Государственного Университета им.Т.Г.Шевченко

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ATtiny2313/V

Programming the EEPROM The EEPROM is organized in pages, see Table 70 on page 161. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” on page 165 for details on Command, Address and Data loading):

1.A: Load Command “0001 0001”.

2.G: Load Address High Byte (0x00 - 0xFF).

3.B: Load Address Low Byte (0x00 - 0xFF).

4.C: Load Data (0x00 - 0xFF).

J:Repeat 3 through 4 until the entire buffer is filled.

K:Program EEPROM page

1.Set BS to “0”.

2.Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low.

3.Wait until to RDY/BSY goes high before programming the next page (See Figure 72 for signal waveforms).

Figure 72. Programming the EEPROM Waveforms

							K
	A	G	B	C	E	B	C	E	L
DATA	0x11	ADDR. HIGH	ADDR. LOW	DATA	XX	ADDR. LOW	DATA	XX
DATA
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2

Reading the Flash	The algorithm for reading the Flash memory is as follows (refer to “Programming the
	Flash” on page 165 for details on Command and Address loading):
	1.	A: Load Command “0000 0010”.
	2.	G: Load Address High Byte (0x00 - 0xFF).
	3.	B: Load Address Low Byte (0x00 - 0xFF).
	4.	Set			to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.
			OE
	5.	Set BS to “1”. The Flash word high byte can now be read at DATA.
	6.	Set			to “1”.
				OE

167

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Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to “Programming the

Flash” on page 165 for details on Command and Address loading):

A: Load Command “0000 0011”.

G: Load Address High Byte (0x00 - 0xFF).

B: Load Address Low Byte (0x00 - 0xFF).

Set

to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at

DATA.

Set

to “1”.

Programming the Fuse Low

The algorithm for programming the Fuse Low bits is as follows (refer to “Programming

Bits

the Flash” on page 165 for details on Command and Data loading):

A: Load Command “0100 0000”.

C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

Give

to go high.

a negative pulse and wait for RDY/BSY

Programming the Fuse High

The algorithm for programming the Fuse High bits is as follows (refer to “Programming

Bits

the Flash” on page 165 for details on Command and Data loading):

A: Load Command “0100 0000”.

C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

Set BS1 to “1” and BS2 to “0”. This selects high data byte.

Give

to go high.

a negative pulse and wait for RDY/BSY

Set BS1 to “0”. This selects low data byte.

Programming the Extended

The algorithm for programming the Extended Fuse bits is as follows (refer to “Program-

Fuse Bits

ming the Flash” on page 165 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse

bit.

3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte.

4. Give

to go high.

a negative pulse and wait for RDY/BSY

5. Set BS2 to “0”. This selects low data byte.

Figure 73. Programming the FUSES Waveforms

			Write Fuse Low byte			Write Fuse high byte			Write Extended Fuse byte
	A	C		A	C		A	C
DATA	0x40	DATA	XX	0x40	DATA	XX	0x40	DATA	XX
DATA

XA1

XA0

BS1

BS2

XTAL1

RDY/BSY

RESET +12V

PAGEL

168 ATtiny2313/V

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ATtiny2313/V

Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 165 for details on Command and Data loading):

1.A: Load Command “0010 0000”.

2.C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any External Programming mode.

3.Give WR a negative pulse and wait for RDY/BSY to go high.

The Lock bits can only be cleared by executing Chip Erase.

Reading the Fuse and Lock

The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming

Bits

the Flash” on page 165 for details on Command loading):

A: Load Command “0000 0100”.

Set

to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can

now be read at DATA (“0” means programmed).

Set

to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can

now be read at DATA (“0” means programmed).

Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits

can now be read at DATA (“0” means programmed).

Set

to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be

read at DATA (“0” means programmed).

Set

to “1”.

Figure 74. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read

Fuse Low Byte

Extended Fuse Byte

DATA

BS2

Lock Bits

BS1

Fuse High Byte

BS2

Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 165 for details on Command and Address loading):

1.A: Load Command “0000 1000”.

2.B: Load Address Low Byte (0x00 - 0x02).

3.Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at DATA.

4.Set OE to “1”.

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Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on page 165 for details on Command and Address loading):

1.A: Load Command “0000 1000”.

2.B: Load Address Low Byte, 0x00.

3.Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4.Set OE to “1”.

Parallel Programming

Figure 75. Parallel Programming Timing, Including some General Timing

Characteristics

Requirements

tXLWL

XTAL1

tXHXL

Data & Contol

tDVXH

tXLDX

(DATA, XA0/1, BS1, BS2)

PAGEL

tBVPH

tPHPL

tPLBX

tBVWL

tWLBX

tWLWH

tPLWL

WLRL

RDY/BSY

tWLRH

Figure 76. Parallel Programming Timing, Loading Sequence with Timing

Requirements(1)

LOAD ADDRESS

LOAD DATA

LOAD DATA LOAD DATA

LOAD ADDRESS

(LOW BYTE)

(HIGH BYTE)

(LOW BYTE)

t XLXH

tXLPH

tPLXH

XTAL1

BS1

PAGEL

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note:

1. The timing requirements shown in Figure 75 (i.e., tDVXH, tXHXL, and tXLDX) also apply

to loading operation.

170 ATtiny2313/V

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ATtiny2313/V

Figure 77. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1)

LOAD ADDRESS

READ DATA

LOAD ADDRESS

(LOW BYTE)

(HIGH BYTE)

(LOW BYTE)

tXLOL

XTAL1

tBVDV

BS1

tOLDV

tOHDZ

ADDR1 (Low Byte)

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

XA0

XA1

Note: 1.

The timing requirements shown in Figure 75 (i.e., tDVXH, tXHXL, and tXLDX) also apply

to reading operation.

Table 76.

Parallel Programming Characteristics, VCC = 5V ± 10%

Symbol

Parameter

Min

Typ

Max

Units

VPP

Programming Enable Voltage

11.5

12.5

IPP

Programming Enable Current

250

µA

tDVXH

Data and Control Valid before XTAL1 High

tXLXH

XTAL1 Low to XTAL1 High

200

tXHXL

XTAL1 Pulse Width High

150

tXLDX

Data and Control Hold after XTAL1 Low

tXLWL

XTAL1 Low to

Low

tXLPH

XTAL1 Low to PAGEL high

tPLXH

PAGEL low to XTAL1 high

150

tBVPH

BS1 Valid before PAGEL High

tPHPL

PAGEL Pulse Width High

150

tPLBX

BS1 Hold after PAGEL Low

tWLBX

BS2/1 Hold after

Low

tPLWL

PAGEL Low to

Low

tBVWL

BS1 Valid to

Low

tWLWH

Pulse Width Low

150

tWLRL

Low

µs

Low to RDY/BSY

tWLRH

High(1)

3.7

4.5

Low to RDY/BSY

tWLRH_CE

High for Chip Erase(2)

7.5

Low to RDY/BSY

tXLOL

XTAL1 Low to

Low

171

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Reading the Flash

Reading the EEPROM

Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 165 for details on Command and Data loading):

Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 165 for details on Command and Address loading):

Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on page 165 for details on Command and Address loading):