- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA2..PA0)
- •Port B (PB7..PB0)
- •Port D (PD6..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •Disclaimer
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •Atomic Byte Programming
- •Split Byte Programming
- •Erase
- •Write
- •I/O Memory
- •General Purpose I/O Registers
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port D
- •Register Description for I/O-Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Overview
- •Functional Descriptions
- •Three-wire Mode
- •SPI Slave Operation Example
- •Two-wire Mode
- •Start Condition Detector
- •Alternative USI Usage
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •Performing a Page Write
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATtiny2313 Rev B
- •ATtiny2313 Rev A
- •Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04
- •Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04
- •Changes from Rev. 2514E-04/04 to Rev. 2514F-08/04
- •Changes from Rev. 2514D-03/04 to Rev. 2514E-04/04
- •Changes from Rev. 2514C-12/03 to Rev. 2514D-03/04
- •Changes from Rev. 2514B-09/03 to Rev. 2514C-12/03
- •Changes from Rev. 2514A-09/03 to Rev. 2514B-09/03
- •Table of Contents
8-bit Timer/Counter0 with PWM
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation. The main features are:
•Two Independent Output Compare Units
•Double Buffered Output Compare Registers
•Clear Timer on Compare Match (Auto Reload)
•Glitch Free, Phase Correct Pulse Width Modulator (PWM)
•Variable PWM Period
•Frequency Generator
•Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
Overview |
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 27. For the |
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actual placement of I/O pins, refer to “Pinout ATtiny2313” on page 2. CPU accessible |
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I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O |
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Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on |
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page 73. |
Figure 27. 8-bit Timer/Counter Block Diagram
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Count |
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Clear |
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Control Logic |
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clkTn |
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Timer/Counter |
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OCRnA |
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DATA |
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Clock Select
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OCnA
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OCnB
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OCnB
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Registers |
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are |
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8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all vis- |
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ible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked |
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with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the |
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figure. |
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The Timer/Counter can be clocked internally, via the prescaler, or by an external clock |
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source on the T0 pin. The Clock Select logic block controls which clock source and edge |
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the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is |
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inactive when no clock source is selected. The output from the Clock Select logic is |
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referred to as the timer clock (clkT0). |
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The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with |
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the Timer/Counter value at all times. The result of the compare can be used by the |
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Waveform Generator to generate a PWM or variable frequency output on the Output |
62 ATtiny2313/V
2543H–AVR–02/05
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ATtiny2313/V |
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Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 64. for details. |
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The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which |
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Definitions |
Many register and bit references in this section are written in general form. A lower case |
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“n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the |
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Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when |
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using the register or bit defines in a program, the precise form must be used, i.e., |
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TCNT0 for accessing Timer/Counter0 counter value and so on. |
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The definitions in Table 33 are also used extensively throughout the document. |
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Table 33. Definitions |
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BOTTOM |
The counter reaches the BOTTOM when it becomes 0x00. |
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MAX |
The counter reaches its MAXimum when it becomes 0xFF (decimal 255). |
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TOP |
The counter reaches the TOP when it becomes equal to the highest |
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value in the count sequence. The TOP value can be assigned to be the |
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fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The |
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assignment is dependent on the mode of operation. |
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Timer/Counter Clock
Sources
Counter Unit
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 80.
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 28 shows a block diagram of the counter and its surroundings.
Figure 28. Counter Unit Block Diagram
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Control Logic |
clkTn |
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Signal description (internal signals): |
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count |
Increment or decrement TCNT0 by 1. |
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direction |
Select between increment and decrement. |
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clear |
Clear TCNT0 (set all bits to zero). |
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clkTn |
Timer/Counter clock, referred to as clkT0 in the following. |
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top |
Signalize that TCNT0 has reached maximum value. |
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bottom |
Signalize that TCNT0 has reached minimum value (zero). |
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2543H–AVR–02/05