- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA2..PA0)
- •Port B (PB7..PB0)
- •Port D (PD6..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •Disclaimer
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •Atomic Byte Programming
- •Split Byte Programming
- •Erase
- •Write
- •I/O Memory
- •General Purpose I/O Registers
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port D
- •Register Description for I/O-Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Overview
- •Functional Descriptions
- •Three-wire Mode
- •SPI Slave Operation Example
- •Two-wire Mode
- •Start Condition Detector
- •Alternative USI Usage
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •Performing a Page Write
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATtiny2313 Rev B
- •ATtiny2313 Rev A
- •Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04
- •Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04
- •Changes from Rev. 2514E-04/04 to Rev. 2514F-08/04
- •Changes from Rev. 2514D-03/04 to Rev. 2514E-04/04
- •Changes from Rev. 2514C-12/03 to Rev. 2514D-03/04
- •Changes from Rev. 2514B-09/03 to Rev. 2514C-12/03
- •Changes from Rev. 2514A-09/03 to Rev. 2514B-09/03
- •Table of Contents
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ATtiny2313/V |
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Electrical Characteristics |
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Absolute Maximum Ratings* |
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Operating Temperature.................................. -55°C to +125°C |
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*NOTICE: |
Stresses beyond those listed under “Absolute |
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Maximum Ratings” may cause permanent dam- |
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Storage Temperature ..................................... -65°C to +150°C |
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age to the device. This is a stress rating only and |
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functional operation of the device at these or |
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Voltage on any Pin except |
RESET |
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other conditions beyond those indicated in the |
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with respect to Ground ................................-0.5V to VCC+0.5V |
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operational sections of this specification is not |
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Voltage on |
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with respect to Ground......-0.5V to +13.0V |
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implied. Exposure to absolute maximum rating |
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RESET |
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conditions for extended periods may affect |
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Maximum Operating Voltage ............................................ 6.0V |
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device reliability. |
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DC Current per I/O Pin ............................................... 40.0 mA |
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DC Current VCC and GND Pins................................ 200.0 mA |
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DC Characteristics |
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T = -40°C to 85°C, V = 1.8V to 5.5V (unless otherwise noted)(1) |
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A |
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CC |
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Symbol |
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Parameter |
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Condition |
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Min. |
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Typ. |
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Max. |
Units |
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VIL |
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Input Low Voltage except |
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VCC = 1.8V - 2.4V |
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-0.5 |
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0.2VCC |
V |
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XTAL1 and RESET pin |
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VCC = 2.4V - 5.5V |
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0.3VCC |
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Input High-voltage except |
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VCC = 1.8V - 2.4V |
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(3) |
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VIH |
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0.7VCC |
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VCC +0.5 |
V |
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(3) |
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XTAL1 and RESET pins |
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VCC = 2.4V - 5.5V |
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0.6VCC |
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VIL1 |
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Input Low Voltage |
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VCC = 1.8V - 5.5V |
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-0.5 |
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0.1VCC |
V |
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XTAL1 pin |
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Input High-voltage |
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VCC = 1.8V - 2.4V |
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(3) |
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VIH1 |
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0.8VCC |
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VCC +0.5 |
V |
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XTAL1 pin |
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VCC = 2.4V - 5.5V |
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(3) |
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0.7VCC |
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VIL2 |
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Input Low Voltage |
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VCC = 1.8V - 5.5V |
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-0.5 |
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0.2VCC |
V |
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RESET |
pin |
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Input High-voltage |
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(3) |
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VIH2 |
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pin |
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VCC = 1.8V - 5.5V |
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0.9VCC |
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VCC +0.5 |
V |
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RESET |
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VIL3 |
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Input Low Voltage |
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VCC = 1.8V - 2.4V |
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-0.5 |
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0.2VCC |
V |
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RESET pin as I/O |
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VCC = 2.4V - 5.5V |
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0.3VCC |
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Input High-voltage |
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VCC = 1.8V - 2.4V |
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(3) |
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VIH3 |
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0.7VCC |
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VCC +0.5 |
V |
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(3) |
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RESET pin as I/O |
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VCC = 2.4V - 5.5V |
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0.6VCC |
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Output Low Voltage(4) |
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I |
OL |
= 10 mA, V |
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= 5V |
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0.7 |
V |
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VOL |
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CC |
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(Port B) |
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IOL = 5 mA, VCC = 3V |
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0.5 |
V |
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VOH |
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Output High-voltage(5) |
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OH |
= -10 mA, V |
CC |
= 5V |
4.2 |
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V |
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(Port B) |
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IOH = -5 mA, VCC = 3V |
2.5 |
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V |
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IIL |
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Input Leakage |
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VCC = 5.5V, pin low |
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1 |
µA |
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Current I/O Pin |
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(absolute value) |
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IIH |
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Input Leakage |
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VCC = 5.5V, pin high |
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1 |
µA |
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Current I/O Pin |
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(absolute value) |
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RRST |
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Reset Pull-up Resistor |
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30 |
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60 |
kΩ |
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Rpu |
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I/O Pin Pull-up Resistor |
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20 |
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50 |
kΩ |
177
2543H–AVR–02/05
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T = -40°C to 85°C, V |
CC |
= 1.8V to 5.5V (unless otherwise noted)(1) |
(Continued) |
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A |
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Symbol |
Parameter |
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Condition |
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Min. |
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Typ. |
Max. |
Units |
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Active 1MHz, VCC = 2V |
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0.35 |
mA |
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Active 4MHz, VCC = 3V |
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2 |
mA |
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Power Supply Current |
Active 8MHz, VCC = 5V |
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6 |
mA |
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Idle 1MHz, VCC = 2V |
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0.08 |
0.2 |
mA |
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Idle 4MHz, VCC = 3V |
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0.41 |
1 |
mA |
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Idle 8MHz, VCC = 5V |
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1.6 |
3 |
mA |
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Power-down mode |
WDT enabled, VCC = 3V |
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< 3 |
6 |
µA |
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WDT disabled, VCC = 3V |
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< 0.5 |
2 |
µA |
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Notes: 1. All DC Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual silicon.
2.“Max” means the highest value where the pin is guaranteed to be read as low.
3.“Min” means the lowest value where the pin is guaranteed to be read as high.
4.Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed:
1] The sum of all IOL, for all ports, should not exceed 60 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.
5.Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed:
1] The sum of all IOH, for all ports, should not exceed 60 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.
External Clock Drive
Waveforms
External Clock Drive
Figure 81. External Clock Drive Waveforms
VIH1
VIL1
Table 80. External Clock Drive (Estimated Values)
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VCC = 1.8 - 5.5V |
VCC = 2.7 - 5.5V |
VCC = 4.5 - 5.5V |
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Symbol |
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Min. |
Max. |
Min. |
Max. |
Min. |
Max. |
Units |
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Oscillator |
0 |
4 |
0 |
10 |
0 |
20 |
MHz |
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1/tCLCL |
Frequency |
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tCLCL |
Clock Period |
250 |
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tCHCX |
High Time |
100 |
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20 |
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tCLCX |
Low Time |
100 |
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40 |
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20 |
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ns |
178 ATtiny2313/V
2543H–AVR–02/05
ATtiny2313/V
Table 80. External Clock Drive (Estimated Values)
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VCC = 1.8 - 5.5V |
VCC = 2.7 - 5.5V |
VCC = 4.5 - 5.5V |
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Symbol |
Parameter |
Min. |
Max. |
Min. |
Max. |
Min. |
Max. |
Units |
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tCLCH |
Rise Time |
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2.0 |
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1.6 |
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0.5 |
µs |
tCHCL |
Fall Time |
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2.0 |
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1.6 |
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0.5 |
µs |
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Change in |
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period from one |
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2 |
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clock cycle to |
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∆tCLCL |
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the next |
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179
2543H–AVR–02/05
Maximum Speed vs. VCC Maximum frequency is dependent on VCC. As shown in Figure 82 and Figure 83, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V.
Figure 82. Maximum Frequency vs. VCC, ATtiny2313V
10 MHz |
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Safe Operating Area |
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4 MHz |
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1.8V |
2.7V |
5.5V |
Figure 83. Maximum Frequency vs. VCC, ATtiny2313
20 MHz
10 MHz
Safe Operating Area
2.7V |
4.5V |
5.5V |
180 ATtiny2313/V
2543H–AVR–02/05