- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA2..PA0)
- •Port B (PB7..PB0)
- •Port D (PD6..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •Disclaimer
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •Atomic Byte Programming
- •Split Byte Programming
- •Erase
- •Write
- •I/O Memory
- •General Purpose I/O Registers
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port D
- •Register Description for I/O-Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Overview
- •Functional Descriptions
- •Three-wire Mode
- •SPI Slave Operation Example
- •Two-wire Mode
- •Start Condition Detector
- •Alternative USI Usage
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •Performing a Page Write
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATtiny2313 Rev B
- •ATtiny2313 Rev A
- •Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04
- •Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04
- •Changes from Rev. 2514E-04/04 to Rev. 2514F-08/04
- •Changes from Rev. 2514D-03/04 to Rev. 2514E-04/04
- •Changes from Rev. 2514C-12/03 to Rev. 2514D-03/04
- •Changes from Rev. 2514B-09/03 to Rev. 2514C-12/03
- •Changes from Rev. 2514A-09/03 to Rev. 2514B-09/03
- •Table of Contents
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ATtiny2313/V |
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Fuse Bits |
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The ATtiny2313 has three Fuse bytes. Table 67 and Table 68 describe briefly the func- |
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tionality of all the fuses and how they are mapped into the Fuse bytes. Note that the |
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fuses are read as logical zero, “0”, if they are programmed. |
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Table 66. Fuse Extended Byte |
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Fuse Extended |
Bit |
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Byte |
No |
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Description |
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Default Value |
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7 |
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– |
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1 |
(unprogrammed) |
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6 |
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– |
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1 |
(unprogrammed) |
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5 |
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– |
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1 |
(unprogrammed) |
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4 |
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– |
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1 |
(unprogrammed) |
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3 |
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– |
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1 |
(unprogrammed) |
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2 |
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– |
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1 |
(unprogrammed) |
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1 |
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– |
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1 |
(unprogrammed) |
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SELFPRGEN |
0 |
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Self Programming Enable |
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1 |
(unprogrammed) |
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Table 67. Fuse High Byte |
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Bit |
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Fuse High Byte |
No |
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Description |
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Default Value |
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DWEN(3) |
7 |
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debugWIRE Enable |
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1 |
(unprogrammed) |
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EESAVE |
6 |
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EEPROM memory is preserved |
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1 |
(unprogrammed, EEPROM |
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through the Chip Erase |
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not preserved) |
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SPIEN(1) |
5 |
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Enable Serial Program and Data |
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0 |
(programmed, SPI prog. |
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Downloading |
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enabled) |
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WDTON(2) |
4 |
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Watchdog Timer always on |
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1 |
(unprogrammed) |
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BODLEVEL2(4) |
3 |
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Brown-out Detector trigger level |
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1 (unprogrammed) |
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BODLEVEL1(4) |
2 |
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Brown-out Detector trigger level |
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1 (unprogrammed) |
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BODLEVEL0(4) |
1 |
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Brown-out Detector trigger level |
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1 (unprogrammed) |
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RSTDISBL(5) |
0 |
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External Reset disable |
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1 |
(unprogrammed) |
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Note: 1. The SPIEN Fuse is not accessible in serial programming mode. |
2.See “Watchdog Timer Control Register - WDTCSR” on page 41 for details.
3.Never ship a product with the DWEN Fuse programmed regardless of the setting of Lock bits. A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes. This may increase the power consumption.
4.See Table 16 on page 34 for BODLEVEL Fuse decoding.
5.See “Alternate Functions of Port A” on page 52 for description of RSTDISBL Fuse.
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2543H–AVR–02/05