- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA2..PA0)
- •Port B (PB7..PB0)
- •Port D (PD6..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •Disclaimer
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •Atomic Byte Programming
- •Split Byte Programming
- •Erase
- •Write
- •I/O Memory
- •General Purpose I/O Registers
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port D
- •Register Description for I/O-Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Overview
- •Functional Descriptions
- •Three-wire Mode
- •SPI Slave Operation Example
- •Two-wire Mode
- •Start Condition Detector
- •Alternative USI Usage
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •Performing a Page Write
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATtiny2313 Rev B
- •ATtiny2313 Rev A
- •Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04
- •Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04
- •Changes from Rev. 2514E-04/04 to Rev. 2514F-08/04
- •Changes from Rev. 2514D-03/04 to Rev. 2514E-04/04
- •Changes from Rev. 2514C-12/03 to Rev. 2514D-03/04
- •Changes from Rev. 2514B-09/03 to Rev. 2514C-12/03
- •Changes from Rev. 2514A-09/03 to Rev. 2514B-09/03
- •Table of Contents
Interrupts
Interrupt Vectors in
ATtiny2313
2543H–AVR–02/05
ATtiny2313/V
This section describes the specifics of the interrupt handling as performed in ATtiny2313. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 11.
Table 21. Reset and Interrupt Vectors
Vector |
Program |
|
|
No. |
Address |
Source |
Interrupt Definition |
|
|
|
|
1 |
0x0000 |
RESET |
External Pin, Power-on Reset, Brown-out Reset, |
|
|
|
and Watchdog Reset |
|
|
|
|
2 |
0x0001 |
INT0 |
External Interrupt Request 0 |
|
|
|
|
3 |
0x0002 |
INT1 |
External Interrupt Request 1 |
|
|
|
|
4 |
0x0003 |
TIMER1 CAPT |
Timer/Counter1 Capture Event |
|
|
|
|
5 |
0x0004 |
TIMER1 COMPA |
Timer/Counter1 Compare Match A |
|
|
|
|
6 |
0x0005 |
TIMER1 OVF |
Timer/Counter1 Overflow |
|
|
|
|
7 |
0x0006 |
TIMER0 OVF |
Timer/Counter0 Overflow |
|
|
|
|
8 |
0x0007 |
USART0, RX |
USART0, Rx Complete |
|
|
|
|
9 |
0x0008 |
USART0, UDRE |
USART0 Data Register Empty |
|
|
|
|
10 |
0x0009 |
USART0, TX |
USART0, Tx Complete |
|
|
|
|
11 |
0x000A |
ANALOG COMP |
Analog Comparator |
|
|
|
|
12 |
0x000B |
PCINT |
Pin Change Interrupt |
|
|
|
|
13 |
0x000C |
TIMER1 COMPB |
Timer/Counter1 Compare Match B |
|
|
|
|
14 |
0x000D |
TIMER0 COMPA |
Timer/Counter0 Compare Match A |
|
|
|
|
15 |
0x000E |
TIMER0 COMPB |
Timer/Counter0 Compare Match B |
|
|
|
|
16 |
0x000F |
USI START |
USI Start Condition |
|
|
|
|
17 |
0x0010 |
USI OVERFLOW |
USI Overflow |
|
|
|
|
18 |
0x0011 |
EE READY |
EEPROM Ready |
|
|
|
|
19 |
0x0012 |
WDT OVERFLOW |
Watchdog Timer Overflow |
|
|
|
|
43
The most typical and general program setup for the Reset and Interrupt Vector
Addresses in ATtiny2313 is:
Address |
Labels Code |
|
Comments |
|
0x0000 |
|
rjmp |
RESET |
; Reset Handler |
0x0001 |
|
rjmp |
INT0 |
; External Interrupt0 Handler |
0x0002 |
|
rjmp |
INT1 |
; External Interrupt1 Handler |
0x0003 |
|
rjmp |
TIM1_CAPT |
; Timer1 Capture Handler |
0x0004 |
|
rjmp |
TIM1_COMPA |
; Timer1 CompareA Handler |
0x0005 |
|
rjmp |
TIM1_OVF |
; Timer1 Overflow Handler |
0x0006 |
|
rjmp |
TIM0_OVF |
; Timer0 Overflow Handler |
0x0007 |
|
rjmp |
USART0_RXC |
; USART0 RX Complete Handler |
0x0008 |
|
rjmp |
USART0_DRE |
; USART0,UDR Empty Handler |
0x0009 |
|
rjmp |
USART0_TXC |
; USART0 TX Complete Handler |
0x000A |
|
rjmp |
ANA_COMP |
; Analog Comparator Handler |
0x000B |
|
rjmp |
PCINT |
; Pin Change Interrupt |
0x000C |
|
rjmp |
TIMER1_COMPB |
; Timer1 Compare B Handler |
0x000D |
|
rjmp |
TIMER0_COMPA |
; Timer0 Compare A Handler |
0x000E |
|
rjmp |
TIMER0_COMPB |
; Timer0 Compare B Handler |
0x000F |
|
rjmp |
USI_START |
; USI Start Handler |
0x0010 |
|
rjmp |
USI_OVERFLOW |
; USI Overflow Handler |
0x0011 |
|
rjmp |
EE_READY |
; EEPROM Ready Handler |
0x0012 |
|
rjmp |
WDT_OVERFLOW |
; Watchdog Overflow Handler |
; |
|
|
|
|
0x0013 |
RESET: ldi |
r16, low(RAMEND); Main program start |
||
0x0014 |
|
out |
SPL,r16 |
Set Stack Pointer to top of |
RAM |
|
|
|
|
0x0015 |
|
sei |
|
; Enable interrupts |
0x0016 |
|
<instr> xxx |
|
|
... |
... |
... ... |
|
44 ATtiny2313/V
2543H–AVR–02/05