402	Analysis and Application of Analog Electronic Circuits

Vo /VR
1.000
0.875					∞ resolution
	N = 3
					line
0.750
	1 LSB
0.625
0.500
0.375
0.250
0.125
0.000
000	001	010	011	100	101	110	111
				{bk}

FIGURE 10.7

I/O characteristic of an ideal 3-bit DAC.

and self-nulling systems. The unity gain small-signal bandwidth (fT) of the AD7845 is 600 kHz; its full-power bandwidth is 250 kHz.

10.3.3Static and Dynamic Characteristics of DACs

Figure 10.7 illustrates the input/output characteristic of an ideal binary, N = 3-bit DAC (in practice the smallest N is typically 8 bits). Note that the analog output has one half LSB of output added to it to minimize conversion error. In general, the LSB and full-scale output of the 3-bit binary input DAC are given by:

			LSB = V /2N			(10.24)
			R
V	= V	R	− LSB/2 = V	R	[1 − 2−(N+1)]	(10.25)
oFS

For the N = 3 DAC, VoFS = VR ∞ 0.9375.

© 2004 by CRC Press LLC

Digital Interfaces

403

Vo /VR
1.000
						∞ resolution
						line
0.875
	N = 3
0.750
				+2.5 LSB DNL
	1 LSB
0.625
							−1.5 LSB INL
0.500					P
	+1 LSB INL
					−0.5 LSB DNL
0.375
	Ideal 3-bit ADC
0.250	(w/ offset)
			Actual 3-bit
			DAC characteristic
0.125
0.000
000	001	010	011	100	101	110	111
				{bk}

FIGURE 10.8

I/O characteristic of a nonideal, 3-bit DAC, showing types of errors. (Adapted from Allen, P.E. and D.R. Holberg, 2002, CMOS Analog Circuit Design, Oxford University Press, New York.)

DAC static errors can be described by the integral nonlinearity (INL) and the differential nonlinearity (DNL). According to Allen and Holberg (2002):

[The] INL is the maximum difference between the actual finite resolution characteristics and the ideal finite resolution characteristic measured vertically. Integral nonlinearity can be expressed as a percentage of the full scale range or in terms of the least significant bit. Integral nonlinearity has several subcategories, which include absolute, best-straight-line, and end-point nonlinearity. The INL of a 3-bit [DAC] characteristic is illustrated in Figure [10.8]. The INL of an N-bit DAC can be expressed as a positive INL and a negative INL. The positive INL is the maximum positive INL. The negative INL is the maximum negative INL. In Figure [10.8], the maximum +INL is 1.0LSB and the maximum −INL is −1.5LSB.

[The] DNL is a measure of the separation between adjacent levels measured at each vertical jump. Differential nonlinearity measures bit-to-bit deviations from ideal output steps, rather than along the entire output range. If Vcx is the actual voltage change on a bit-to-bit basis and Vs is the ideal change, then the differential nonlinearity can be expressed as

© 2004 by CRC Press LLC

404	Analysis and Application of Analog Electronic Circuits
DNL =	Vcx − Vs	∞ 100%	= V	V	− 1 LSBs	[10.26]
	Vs		( cx	s	)
For an N-bit DAC and a full-scale voltage range of VFSR,
	V = V		2N			[10.27]
		s FSR

Figure [10.8] also illustrates differential nonlinearity. Note that DNL is a measure of the step size and is totally independent of how far the actual step change may be from the infinite resolution characteristic at the jump. The change from 101 to 110 results in a maximum +DNL of 2.5LSBs (Vcx/Vs = 2.5LSBs). The maximum negative DNL is found when the digital input code changes from 011 to 100. The change is −0.5 LSB (Vcx/Vs = −0.5LSB), which gives a DNL of −0.5LSB. It is of interest to note that as the digital input code changes from 100 to 101, no change occurs (point P). Because we know that a change should have occurred, we can say that the DNL at point P is −0.5LSB.

Dynamic DAC characteristics of DACs limit the speed at which they can convert digital words to analog signals. If a DAC IC has an on-chip op amp for current-to-voltage conversion, the op amp’s fT and slew rate, η, provide one factor that limits conversion speed. Another factor comes from on-chip parasitic capacitances that shunt all resistors and transistors to substrate ground. Conversion speed is also limited by the rate at which MOS and/or BJT switches can turn on and off. Glitches — unwanted (artifactual) transients on the DAC output immediately following a digital word input — are another problem with high-speed DACs. Franco (1988) describes their origin and a cure:

… these are due to the internal circuitry’s nonuniform response to input bit changes and to poor synchronization of the bit changes themselves. For instance, if during the center-scale transition from 011…1 to 100…0 the MSB is perceived as going on before (after) all other bits go off, the output will momentarily [try to] swing to full-scale (to zero), thus causing an output glitch.

Glitches are of particular concern in CRT display applications. Filtering doesn’t solve the problem since the area under the glitch is integrated and carried over subsequent steps [i.e., as the filter’s impulse response], which will therefore also be in error. Glitches can be minimized either by synchronizing the input bit changes with a high-speed parallel latch register, or by processing the DAC output with a[n] S/H [sample and hold] deglitcher circuit. The circuit is switched to hold mode just prior to the input code change and is returned to the track mode only after the DAC gas settle[s] to its new level, thus preventing any glitches from reaching the output.

© 2004 by CRC Press LLC