406	Analysis and Application of Analog Electronic Circuits

Note that other more sophisticated holds exist; their realization is at the expense of some circuit complexity, however. For example, the firstdifference extrapolator hold that generates linear slope transitions between sampling instants (instead of steps) can be realized with three DACs, a resettable analog integrator, and an analog adder (Northrop, 1990). Its transfer function can be shown to be:

	H	(s) =	1− e−sT	+	1− 2e−sT + e−2sT	−	(1− e−sT )e−sT	(10.32)
			s		s2		s
	e

10.5 Analog-to-Digital Converters (ADCs)

10.5.1Introduction

Although the technology for DACs is relatively simple, there are many diverse kinds of ADCs and ADC algorithms. The five major categories of ADC are:

1.Tracking (servo) converters

2.Successive approximation converters

3.Integrating converters

4.Flash (parallel) converters

5.Oversampled (sigma–delta) converters

Next, each category will be examined and a description of how it works given.

Figure 10.9 shows the transfer characteristic of a 3-bit binary-output ADC. Note that an infinite-resolution analog signal, x(t), is quantized into eight 3- bit binary words, depending on its value. Figure 10.10 illustrates the normalized quantization error, (NQE) ∫ ve/LSB, of this converter; the quantization error voltage is given by:

N

vc = vx − VFS bk 2−k = vx − VFS(b12−1 + b2 2−2 + b3 2−3 ), for N = 3. (10.33)

k =1

Note that the NQE is bounded by plus or minus one half LSB except for

vx/VFS ≥ 7/8, where it reaches +1 LSB at vx/VFS = 1. 1 LSB = VFS/23 = VFS/8 for this 3-bit ADC.

© 2004 by CRC Press LLC

Digital Interfaces

407

{bk}	3-bit binary
	output code
111						∞ resolution
						line
110
		1 LSB
101
100
011
010
001
000
0.000		0.125	0.250	0.375	0.500	0.625	0.750	0.875	1.000
					vx /VFS

(Normalized input voltage)

FIGURE 10.9

Transfer characteristic of an ideal 3-bit binary-output ADC.

10.5.2The Tracking (Servo) ADC

The first ADC considered is the tracking (servo) ADC, aka the counting ADC. A block diagram for this ADC is shown in Figure 10.11. When conversion is initiated, the up/down counter is reset and then counts up. The up/down counter’s digital output goes to a DAC. The DAC’s voltage output ramps up at a rate easily shown to be:

η = VoFS (2N Tc ) V sec

(10.34)

where N is the number of bits of the DAC and U/D counter and Tc is the clock period.

V is generally made equal to V		. If N = 10 bits, T = 5 ∞ 10−7 sec (f =
oFS	xmax	c	∞ 104	c
2 MHz), and V	= 10 V, then the V slew rate is η = 1.953			V/sec.
omax	o

By resetting the counter following each 10-V conversion, approximately 1,950 10-V conversions can be made per second. If conversion is not stoppedwhen the comparator output goes LO (Vo > Vx) and the counter is not reset, then the counter will increment down by 1 LSB at the next clock cycle,

© 2004 by CRC Press LLC

408	Analysis and Application of Analog Electronic Circuits

Quantization
error (LSB)
1.5
	L	SB
1.0
0.5
0
− 0.5
− 1.0
− 1.5
0.000	0.125	0.250	0.375	0.500	0.625	0.750	0.875	1.000
				Vo /VFS

Input voltage

FIGURE 10.10

Normalized quantization error vs. input voltage for an ideal 3-bit binary ADC.

causing Vo to decrease by 1 LSB, thus bringing Vo < Vx; the comparator then goes HI and the next clock pulse increments the counter up, so Vo then exceeds Vx. The process repeats cyclically, generating a steady-state 1-LSB dither in the digital output.

When this ADC is used in the tracking mode to improve conversion speed, the LSB output is not used in order to avoid the steady-state dither. If the ADC is reset after each conversion, the end of conversion (EOC) signal occurs when Vo > Vx by 1 LSB the first time after conversion is initiated. Although this mode of operation avoids dither, it is slower and still has a conversion error between 0 and +1 LSB.

The servo counting ADC is well suited for data conversion of DC or low-frequency AC signals. It is also easy to implement in hardware (ICs). One disadvantage is that conversion time depends on the value of vx/Vxmax, i.e., it is variable. Another disadvantage is the LSB dither seen in the steady-state tracking mode.

10.5.3The Successive Approximation ADC

Like the servo counting ADC, the successive approximation ADC (SAADC) uses a comparator and a DAC in a closed-loop architecture, as shown in Figure 10.12. The conversion cycle for a 10-bit SAADC begins with a start signal from the controlling computer’s I/O interface at t = nT. Start causes the analog input signal, Vx, to be held at [Vx(nT)] and the counter’s

© 2004 by CRC Press LLC

	Digital Interfaces			409
	+5 V		EOC CON	RST
	Vx	(1,0)	Control
	Comp.			Clock
			logic
	Vo
		N	U/D	RST
	N-bit DAC		Up/Down
			counter	CLK

N − 1 bits out

(no LSB)

	LSB dither
Vxo	Vx
	Vo
	Maximum η
	t
0 0

FIGURE 10.11

Top: block diagram of a tracking or servo ADC. Bottom: DAC output of the servo ADC showing numerical slew-rate limiting and dither.

output register is cleared (all bk 0 except for b1 = 0 (MSB)). This action causes the DAC output, Vo, to go to 512VR/1024 = VR/2. The comparator subtracts this Vo from [Vx(nT)] and performs the operation,

Q = sgn([Vx (nT)]− VR 2)

(10.35)

If Q = 1, then b1 is kept 1 (HI); if Q = −1, then b1 is set to 0 (LO). Next, b2 is set to 1 (b1 retains the value determined in the first cycle). Now the DAC output is Vo = VR (b1/2 + 1/22). The comparator tests to see if sgn{[Vx ((n + 1)T] − Vo} = 1. If yes, b2 stays at 1, if no, b2 0, completing the second bit’s conversion cycle. Now b3 1 and Vo = VR (b1/2 + b2/4 + 1/23) and the process continues. Q = sgn{Vx ((n + 2)T] − Vo} is tested, etc. until all 10 bits have been tested. Figure 10.13, adapted from Northrop (1990), illustrates a logical flowchart for the operation of a 10-bit SAADC; note b1 = MSB and b10 = LSB.

© 2004 by CRC Press LLC