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Digital Interfaces

427

^

 

x(n)

y(n)

x(n)

H(z)

e(n)

FIGURE 10.29

Block diagram of a model in which quantization noise is added to a noise-free sampled signal at the input to a digital filter.

σq2 is the variance of the white quantization noise and the variance of the filter’s output noise can be shown to be expressed as (Northrop, 2003):

 

 

σy2 = σq2 h2

(k)

(10.57)

k = 0

10.7 Chapter Summary

Digital interfaces generate sampled data when they periodically convert an analog signal to numerical form or numerical data to an analog voltage or current. Sampled data are subject to the sampling theorem, which describes the conditions under which unwanted aliasing can take place. This chapter described sampling as impulse modulation and showed how sampled data can be described in the frequency domain by a repeated spectrum Poisson sum. In the frequency domain, aliasing was shown to exist when the edges of the repeated spectra in the Poisson sum overlapped. This overlapping occurred when the power density spectrum of the sampled analog signal contained significant power above one half the sampling frequency, also known as the Nyquist frequency.

Digital-to-analog converters (DACs) were next covered and their circuit architecture and factors affecting the speed of conversion were described. Hold circuits were also described; the transfer function of the zero-order hold and a simple extrapolator hold were derived.

Many types of analog-to-digital converters (ADCs) were described, including the tracking or servo ADC; the successive approximation ADC; integrating ADCs; and flash ADCs. Flash ADCs were seen to be the fastest because they convert in parallel.

Finally, quantization noise was described and an expression for ADC SNR due to quantiza;-tion noise was derived as a function of the number of binary bits in the converted signal. The more bits there are, the higher the ADC’s SNR is.

© 2004 by CRC Press LLC

428

Analysis and Application of Analog Electronic Circuits

Home Problems

10.1A 16-bit ADC is used to convert an audio signal ranging over ±1 V.

a.Find the size of the quantization step, q, required.

b.Find the RMS quantization noise associated with full-scale operation of this ADC.

c.Let vin(t) = 1 sin(ωo t). Find the RMS SNR at the ADC output in decibels.

10.2Consider the 4-bit resistive ladder DAC shown in Figure P10.2.

a.Use superposition to find an expression for Vo = f(Io, I1, I2, I3). Let R = 1 kΩ and Io = 1 mA dc.

b.What values should I1, I2, and I3 have to make a binary DAC? What is the max. Vo?

 

R

2R

2R

R

 

 

 

R

R

R

ID

V3

 

V2

V1

 

 

 

 

 

 

 

 

 

Vo

I3

I2

I1

 

IOA

 

I0

FIGURE P10.2

10.3 Refer to the text Figure 10.5 for the switched weighted capacitor DAC; in this problem you will examine the dynamics of this system. A simplified circuit is shown in Figure P10.3. In this circuit, k = 0, 1, 2, …, N − 1. The op amp is characterized by Rin = •; IB = Vos = Rout = 0; and Vo = (−Kvo ωb)/(s + ωb).

a. Find an algebraic expression for Vo/VR(s).

b. Assume VR(s) = VRo/s (step input). Give an expression for Vo(s). Plot and dimension a general vo(t).

c. Let k = 0, N = 8; sketch and dimension vo(t). d. Let k = N − 1 = 7; sketch and dimension vo(t).

e. Find a general expression for the maximum slope of vo(t) in terms of k and other system parameters.

f. Let VRo = 1 V and the op amp’s GBWP = Kvo ωb = 3 ∞ 108. Find

°

Vomax for k = 0 and k = 7. What must the op amp’s slew rate be to avoid slew-rate limiting of Vo(t)?

© 2004 by CRC Press LLC

Digital Interfaces

 

429

 

2N C

 

 

2k C

 

Vi

 

OA

Vo

VR

 

 

+

 

 

FIGURE P10.3

10.4Figure P10.4 illustrates an N = 8-bit MOSFET current-scaling DAC. The feedback action of the left-hand op amp forces the Q1 drain current to be ID = VR/(2N R). The left-hand op amp also puts all the connected FET gates at virtual ground (0). The right-hand op amp forces the FET drains connected to it to be at virtual ground (0). Because all of the MOSFETs are matched and they all have the same drain, gate, and source voltage, they all have the same drain current, ID. Write an expression for Vo = f ({bk}, VR).

R

VR

 

 

 

 

 

 

 

 

Vo

2N R

0

1

0

1

0

1

0

1

IOA

 

(0)

b0

2N 1 ID

 

bN 3 22 ID

bN 2

21 ID

bN 1

ID

 

 

 

 

 

 

 

 

 

 

ID

 

 

 

 

 

 

 

 

 

 

 

 

+ VGS

 

 

 

+

 

 

 

Q1

 

 

 

 

VGS

 

 

IOA

 

 

 

 

 

 

 

 

 

 

 

2N 1 matched FETs

22 matched FETs

21 matched FETs

 

 

FIGURE P10.4

10.5Figure P10.5 illustrates an N-bit binary-weighted charge amplifier DAC. Note that the ideal op amp’s summing junction is at virtual ground, so the net charge flowing into the kth input capacitor when bk = 1 must also equal the charge accumulated in CF = 2C/K. That is, Qk = VRC/2k = QF = Vo 2C/K. Write an expression for Vo = f ({bk}, VR, K); use superposition.

10.6An 8-bit successive approximation ADC has a reference voltage,VR, set to 10.0 V at 25C. Find the maximum allowable temperature coefficient of VR in μV/C that will allow an error of no more than plus or minus one half LSB over an operating temperature range of 0 to 50C.

10.7A 100-mV peak-to-peak sinusoidal signal is the input to a 12-bit ADC that has a bipolar offset binary output and a full-scale input range of ±2.5 V.

© 2004 by CRC Press LLC

430

Analysis and Application of Analog Electronic Circuits

 

1

b0

 

 

 

0

C

 

 

 

 

 

 

VR

1

b1

 

 

 

 

 

2C/K

 

 

0

C/2

 

 

 

 

 

 

 

1

b2

 

 

 

 

 

(0)

 

 

0

C/4

IOA

Vo

 

 

 

1

bN 1

 

 

 

0

C/2N 1

 

 

 

 

 

 

FIGURE P10.5

a.Find the output RMS SNR in decibels when the input is a 2.5-V peak sinewave.

b.Find the output RMS SNR in decibels when the input is a 50-mV peak sinewave.

10.8A unipolar 3-bit successive-approximation ADC has VR = 8.0 V and a ½ LSB offset as shown in text Figure 10.27. Vin = 2.832 V. Find the LSB voltage as well as the intermediate and final DAC output voltages during conversion.

10.9Explain the differences between Nyquist-rate data converters and oversampling data converters.

10.10Find the maximum magnitude of quantization error for a 10-bit ADC with VR = 10 V and one half LSB absolute accuracy.

© 2004 by CRC Press LLC