- •Features
- •Pin Configurations
- •Disclaimer
- •Overview
- •Block Diagram
- •AT90S8535 Compatibility
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog-to-Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •SS Pin Functionality
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •SCL and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •Boot Loader Features
- •Application Section
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •Active Supply Current
- •Idle Supply Current
- •Power-Save Supply Current
- •Standby Supply Current
- •Pin Pullup
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega8535 all rev.
- •Datasheet Change Log for ATmega8535
- •Changes from Rev. 2502E-12/03 to Rev. 2502F-06/04
- •Changes from Rev. 2502D-09/03 to Rev. 2502E-12/03
- •Changes from Rev. 2502C-04/03 to Rev. 2502D-09/03
- •Changes from Rev. 2502B-09/02 to Rev. 2502C-04/03
- •Changes from Rev. 2502A-06/02 to Rev. 2502B-09/02
- •Table of Contents
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ATmega8535(L) |
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Internal Voltage |
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ATmega8535 features an internal bandgap reference. This reference is used for Brown- |
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Reference |
out Detection, and it can be used as an input to the Analog Comparator or the ADC. The |
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2.56V reference to the ADC is generated from the internal bandgap reference. |
Voltage Reference Enable The voltage reference has a start-up time that may influence the way it should be used. Signals and Start-up Time The start-up time is given in Table 16. To save power, the reference is not always turned on. The reference is on during the following situations:
1.When the BOD is enabled (by programming the BODEN Fuse).
2.When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).
3.When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.
Watchdog Timer
Table 16. Internal Voltage Reference Characteristics(1)
Symbol |
Parameter |
Min |
Typ |
Max |
Units |
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VBG |
Bandgap reference voltage |
1.15 |
1.23 |
1.35 |
V |
tBG |
Bandgap reference start-up time |
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40 |
70 |
µs |
IBG |
Bandgap reference current consumption |
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10 |
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µA |
Note: 1. |
Values are guidelines only. |
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The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 18 on page 41. The WDR – Watchdog Reset
– instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega8535 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to page 38.
To prevent unintentional disabling of the Watchdog or unintentional change of Time-out period, three different safety levels are selected by the Fuses S8535C and WDTON as shown in Table 17. Safety level 0 corresponds to the setting in AT90S8535. There is no restriction on enabling the WDT in any of the safety levels.
39
2502F–AVR–06/04
Table 17. WDT Configuration as a Function of the Fuse Settings of M103C and WDTON
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How to |
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Safety |
WDT Initial |
How to Disable |
Change |
S8535C |
WDTON |
Level |
State |
the WDT |
Time-out |
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Unprogrammed |
Unprogrammed |
1 |
Disabled |
Timed |
Timed |
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sequence |
sequence |
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Unprogrammed |
Programmed |
2 |
Enabled |
Always enabled |
Timed |
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sequence |
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Programmed |
Unprogrammed |
0 |
Disabled |
Timed |
No |
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sequence |
restriction |
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Programmed |
Programmed |
2 |
Enabled |
Always enabled |
Timed |
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sequence |
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Figure 21. Watchdog Timer
WATCHDOG
OSCILLATOR
Watchdog Timer Control
Register – WDTCR
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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– |
– |
– |
WDCE |
WDE |
WDP2 |
WDP1 |
WDP0 |
WDTCR |
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Read/Write |
R |
R |
R |
R/W |
R/W |
R/W |
R/W |
R/W |
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Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega8535 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In Safety Level 1 and 2, this bit must also be set when changing the prescaler bits. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 43.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared
40 ATmega8535(L)
2502F–AVR–06/04
ATmega8535(L)
if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed:
1.In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts.
2.Within the next four clock cycles, write a logic 0 to WDE. This disables the watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 43.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
Timeout Periods are shown in Table 18.
Table 18. Watchdog Timer Prescale Select(1)
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Number of WDT |
Typical Time-out |
Typical Time-out |
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WDP2 |
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WDP1 |
WDP0 |
Oscillator Cycles |
at VCC = 3.0V |
at VCC = 5.0V |
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0 |
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0 |
0 |
16K |
(16,384) |
17.1 ms |
16.3 ms |
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0 |
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0 |
1 |
32K |
(32,768) |
34.3 ms |
32.5 ms |
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0 |
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1 |
0 |
64K |
(65,536) |
68.5 ms |
65 ms |
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0 |
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1 |
1 |
128K |
(131,072) |
0.14 s |
0.13 s |
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1 |
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0 |
0 |
256K |
(262,144) |
0.27 s |
0.26 s |
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1 |
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0 |
1 |
512K |
(524,288) |
0.55 s |
0.52 s |
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1 |
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1 |
0 |
1,024K |
(1,048,576) |
1.1 s |
1.0 s |
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1 |
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1 |
1 |
2,048K |
(2,097,152) |
2.2 s |
2.1 s |
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Note: |
1. Values are guidelines only. |
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41
2502F–AVR–06/04
The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
Assembly Code Example
WDT_off:
; Reset WDT
wdr
; Write logical one to WDCE and WDE in r16, WDTCR
ori r16, (1<<WDCE)|(1<<WDE) out WDTCR, r16
; Turn off WDT
ldi r16, (0<<WDE) out WDTCR, r16
ret
C Code Example
void WDT_off(void)
{
/* Reset WDT */
_WDR()
/* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */ WDTCR = 0x00;
}
42 ATmega8535(L)
2502F–AVR–06/04