ATmega8535(L)

Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to “Programming the

Flash” on page 240 for details on Command and Address loading):

1.

A: Load Command “0000 0011”.

2.

G: Load Address High Byte (0x00 - 0xFF).

3.

B: Load Address Low Byte (0x00 - 0xFF).

4.

Set

to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at

OE

DATA.

5.

Set

to “1”.

OE

Programming the Fuse Low

The algorithm for programming the Fuse Low bits is as follows (refer to “Programming

Bits

the Flash” on page 240 for details on Command and Data loading):

1.

A: Load Command “0100 0000”.

2.

C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3.

Set BS1 to “0” and BS2 to “0”. This selects low data byte.

4.

Give

to go high.

WR

a negative pulse and wait for RDY/BSY

Programming the Fuse High

The algorithm for programming the Fuse high bits is as follows (refer to “Programming

Bits

the Flash” on page 240 for details on Command and Data loading):

1.

A: Load Command “0100 0000”.

2.

C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3.

Set BS1 to “1” and BS2 to “0”. This selects high data byte.

4.

Give

to go high.

WR

a negative pulse and wait for RDY/BSY

5.

Set BS1 to “0”. This selects low data byte.

Figure 119. Programming the Fuses Waveforms

			Write Fuse Low byte			Write Fuse High byte
	A	C		A	C
DATA	$40	DATA	XX	$40	DATA	XX

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

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Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 240 for details on Command and Data loading):

1.A: Load Command “0010 0000”.

2.C: Load Data Low Byte. Bit n = “0” programs the Lock bit.

3.Give WR a negative pulse and wait for RDY/BSY to go high.

The Lock bits can only be cleared by executing Chip Erase.

Reading the Fuse and Lock

The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming

Bits

the Flash” on page 240 for details on Command loading):

1.

A: Load Command “0000 0100”.

2.

Set

to “0”, BS2 to “0”, and BS1 to “0”. The status of the Fuse Low bits can

OE

now be read at DATA (“0” means programmed).

3.

Set

to “0”, BS2 to “1”, and BS1 to “1”. The status of the Fuse High bits can

OE

now be read at DATA (“0” means programmed).

4.

Set

to “0”, BS2 to “0”, and BS1 to “1”. The status of the Lock bits can now be

OE

read at DATA (“0” means programmed).

5.

Set

to “1”.

OE

Figure 120. Mapping Between BS1, BS2 and the Fuseand Lock Bits During Read

Fuse Low Byte

0

DATA

1

Lock Bits				0				BS1
Fuse High Byte					1
	BS2

Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 240 for details on Command and Address loading):

1.A: Load Command “0000 1000”.

2.B: Load Address Low Byte (0x00 - 0x02).

3.Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at DATA.

4.Set OE to “1”.

Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on page 240 for details on Command and Address loading):

1.A: Load Command “0000 1000”.

2.B: Load Address Low Byte, 0x00.

3.Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4.Set OE to “1”.

244 ATmega8535(L)

2502F–AVR–06/04

ATmega8535(L)

Parallel Programming

Figure 121. Parallel Programming Timing, Including some General Timing

Characteristics

Requirements

tXLWL

XTAL1

tXHXL

Data & Contol

tDVXH

tXLDX

(DATA, XA0/1, BS1, BS2)

tBVPH

tPLBX

tBVWL

tWLBX

PAGEL

tPHPL

tWLWH

WR

tPLWL

WLRL

RDY/BSY

tWLRH

Figure 122. Parallel Programming Timing, Loading Sequence with Timing

Requirements(1)

LOAD ADDRESS

LOAD DATA

LOAD DATA LOAD DATA

LOAD ADDRESS

(LOW BYTE)

(LOW BYTE)

(HIGH BYTE)

(LOW BYTE)

t XLXH

tXLPH

tPLXH

XTAL1

BS1

PAGEL

DATA

ADDR0 (low byte)

DATA (low byte)

DATA (high byte)

ADDR1 (low byte)

XA0

XA1

Note:

1. The timing requirements shown in Figure 121 (i.e. tDVXH, tXHXL, and tXLDX) also apply

to loading operation.

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Figure 123. Parallel Programming Timing, Reading Sequence (within the same Page) with Timing Requirements(1)

LOAD ADDRESS

READ DATA

READ DATA

LOAD ADDRESS

(LOW BYTE)

(LOW BYTE)

(HIGH BYTE)

(LOW BYTE)

tXLOL

XTAL1

BS1

tBVDV

tOLDV

OE

tOHDZ

ADDR1 (low byte)

DATA

ADDR0 (low byte)

DATA (low byte)

DATA (high byte)

XA0

XA1

Note:

1. The timing requirements shown in Figure 121 (i.e. tDVXH, tXHXL, and tXLDX) also apply

to reading operation.

246 ATmega8535(L)

2502F–AVR–06/04

ATmega8535(L)

Table 106.

Parallel Programming Characteristics, VCC = 5V ± 10%

Symbol

Parameter

Min

Typ

Max

Units

VPP

Programming Enable Voltage

11.5

12.5

V

IPP

Programming Enable Current

250

µA

tDVXH

Data and Control Valid before XTAL1 High

67

ns

tXLXH

XTAL1 Low to XTAL1 High

200

ns

tXHXL

XTAL1 Pulse Width High

150

ns

tXLDX

Data and Control Hold after XTAL1 Low

67

ns

tXLWL

XTAL1 Low to

Low

0

ns

WR

tXLPH

XTAL1 Low to PAGEL High

0

ns

tPLXH

PAGEL low to XTAL1 High

150

ns

tBVPH

BS1 Valid before PAGEL High

67

ns

tPHPL

PAGEL Pulse Width High

150

ns

tPLBX

BS1 Hold after PAGEL Low

67

ns

tWLBX

BS2/1 Hold after

Low

67

ns

WR

tPLWL

PAGEL Low to

Low

67

ns

WR

tBVWL

BS1 Valid to

Low

67

ns

WR

tWLWH

Pulse Width Low

150

ns

WR

tWLRL

Low

0

1

µs

WR

Low to RDY/BSY

t

High(1)

3.7

4.5

ms

WLRH

WR

Low to RDY/BSY

tWLRH_CE

High for Chip Erase(2)

7.5

9

ms

WR

Low to RDY/BSY

tXLOL

XTAL1 Low to

Low

0

ns

OE

tBVDV

BS1 Valid to DATA Valid

0

250

ns

tOLDV

Low to DATA Valid

250

ns

OE

tOHDZ

High to DATA Tri-stated

250

ns

OE

Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.

2.tWLRH_CE is valid for the Chip Erase command.

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