Two-wire Serial Interface Characteristics

Table 112 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8535 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 127.

Table 112. Two-wire Serial Bus Requirements

Symbol

Parameter

Condition

Min

Max

Units

VIL

Input Low Voltage

-0.5

0.3 VCC

V

VIH

Input High Voltage

0.7 VCC

VCC + 0.5

V

(1)

Hysteresis of Schmitt Trigger Inputs

(2)

–

V

Vhys

0.05 VCC

(1)

Output Low Voltage

3 mA sink current

0

0.4

V

VOL

(1)

Rise Time for both SDA and SCL

20 + 0.1C

(3)(2)

300

ns

tr

b

(1)

Output Fall Time from V

IHmin

to V

ILmax

10 pF < C < 400 pF(3)

20 + 0.1C

(3)(2)

250

ns

tof

b

b

tSP(1)

Spikes Suppressed by Input Filter

0

50(2)

ns

Ii

Input Current each I/O Pin

0.1VCC < Vi < 0.9VCC

-10

10

µA

C (1)

Capacitance for each I/O Pin

–

10

pF

i

f

SCL

SCL Clock Frequency

f

CK

(4) > max(16f , 250kHz)(5)

0

400

kHz

SCL

fSCL ≤ 100 kHz

VCC – 0.4V

1000ns

Ω

----------------------------

-------------------

Rp

Value of Pull-up resistor

3mA

Cb

fSCL > 100 kHz

VCC – 0.4V

300ns

Ω

----------------------------

---------------

3mA

Cb

tHD;STA

Hold Time (Repeated) START Condition

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

f

≤ 100 kHz(6)

4.7

–

µs

tLOW

Low Period of the SCL Clock

SCL

fSCL > 100 kHz(7)

1.3

–

µs

tHIGH

High Period of the SCL clock

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

tSU;STA

Set-up Time for a Repeated START

fSCL ≤ 100 kHz

4.7

–

µs

Condition

fSCL > 100 kHz

0.6

–

µs

tHD;DAT

Data hoLd Time

fSCL ≤ 100 kHz

0

3.45

µs

fSCL > 100 kHz

0

0.9

µs

tSU;DAT

Data Setup Time

fSCL ≤ 100 kHz

250

–

ns

fSCL > 100 kHz

100

–

ns

tSU;STO

Setup Time for STOP Condition

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

tBUF

Bus Free Time between a STOP and START

fSCL ≤ 100 kHz

4.7

–

µs

Condition

fSCL > 100 kHz

1.3

–

µs

Notes: 1. In ATmega8535, this parameter is characterized and not 100% tested.

2.Required only for fSCL > 100 kHz.

3.Cb = capacitance of one bus line in pF.

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4.fCK = CPU clock frequency.

5.This requirement applies to all ATmega8535 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement.

6.The actual low period generated by the ATmega8535 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.

7.The actual low period generated by the ATmega8535 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega8535 devices connected to the bus may communicate at full speed (400 kHz) with other ATmega8535 devices, as well as any other device with a proper tLOW acceptance margin.

Figure 127. Two-wire Serial Bus Timing

tof

tHIGH

tr

SCL

tLOW

tLOW

tSU;STA

tHD;STA

tHD;DAT

t

SDA

SU;DAT

tSU;STO

tBUF

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SPI Timing

Characteristics

See Figure 128 and Figure 129 for details.

Table 113. SPI Timing Parameters

		Description				Mode	Min	Typ	Max
1		SCK period				Master		See Table 59
2		SCK high/low				Master		50% duty cycle
3		Rise/Fall time				Master		TBD
4		Setup				Master		10
5		Hold				Master		10
6		Out to SCK				Master		5 • tSCK
7		SCK to out				Master		10
8		SCK to out high				Master		10
9		SS low to out				Slave		15		ns
10		SCK period				Slave	4 • tck
11		SCK high/low				Slave	2 • tck
12		Rise/Fall time				Slave		TBD
13		Setup				Slave	10
14		Hold				Slave	tck
15		SCK to out				Slave		15
16		SCK to			high	Slave	20
				SS
17			high to tri-state			Slave		10
		SS
18		SS low to SCK				Slave	2 • tck

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Figure 128. SPI Interface Timing Requirements (Master Mode)

SS

6

1

	SCK
	(CPOL = 0)
			2	2
	SCK
	(CPOL = 1)
	4	5		3
	MISO	MSB	...	LSB
	(Data Input)
			7	8
	MOSI	MSB	...	LSB
	(Data Output)

Figure 129. SPI Interface Timing Requirements (Slave Mode)

	18
	SS
	9			10	16
	SCK
	(CPOL = 0)
			11	11
	SCK
	(CPOL = 1)
	13	14			12
	MOSI	MSB	...	LSB
	(Data Input)
			15		17
	MISO	MSB	...	LSB	X
	(Data Output)

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ADC Characteristics – Preliminary Data

Table 114. ADC Characteristics, Single Ended Channels

Symbol	Parameter	Condition	Min(1)	Typ(1)	Max(1)	Units
	Resolution	Single Ended Conversion		10		Bits
		Single Ended Conversion
		VREF = 4V, VCC = 4V		1.5		LSB
		ADC clock = 200 kHz
		Single Ended Conversion
		VREF = 4V, VCC = 4V		3		LSB
	Absolute Accuracy	ADC clock = 1 MHz
		Single Ended Conversion
	(Including INL, DNL, Quantization Error, Gain
		VREF = 4V, VCC = 4V
	and Offset Error)			1.5		LSB
		ADC clock = 200 kHz
		Noise Reduction mode
		Single Ended Conversion
		VREF = 4V, VCC = 4V		3		LSB
		ADC clock = 1 MHz
		Noise Reduction mode
		Single Ended Conversion
	Integral Non-Linearity (INL)	VREF = 4V, VCC = 4V		0.75		LSB
		ADC clock = 200 kHz
		Single Ended Conversion
	Differential Non-Linearity (DNL)	VREF = 4V, VCC = 4V		0.25		LSB
		ADC clock = 200 kHz
		Single Ended Conversion
	Gain Error	VREF = 4V, VCC = 4V		0.75		LSB
		ADC clock = 200 kHz
		Single Ended Conversion
	Offset error	VREF = 4V, VCC = 4V		0.75		LSB
		ADC clock = 200 kHz
	Clock Frequency		50		1000	kHz
	Conversion Time		13		260	µs
AVCC	Analog Supply Voltage		VCC - 0.3(2)		VCC + 0.3(3)	V
VREF	Reference Voltage		2.0		AVCC	V
VIN	Input Voltage		GND		VREF	V
	ADC Conversion Output		0		1023	LSB
	Input Bandwidth			38.5		kHz
VINT	Internal Voltage Reference		2.3	2.56	2.7	V
RREF	Reference Input Resistance			32		kΩ
RAIN	Analog Input Resistance			100		MΩ

Notes: 1. Values are guidelines only.

2.Minimum for AVCC is 2.7V.

3.Maximum for AVCC is 5.5V

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Table 115. ADC Characteristics, Differential Channels

Symbol	Parameter	Condition		Min(1)	Typ(1)	Max(1)	Units
		Gain =	1x			10	Bits
	Resolution	Gain =	10x			10	Bits
		Gain = 200x				10	Bits
		Gain = 1x
		VREF = 4V, VCC = 5V			18		LSB
		ADC clock = 50 - 200 kHz
		Gain = 10x
	Absolute Accuracy	VREF = 4V, VCC = 5V			18		LSB
		ADC clock = 50 - 200 kHz
		Gain = 200x
		VREF = 4V, VCC = 5V			6		LSB
		ADC clock = 50 - 200 kHz
		Gain = 1x
		VREF = 4V, VCC = 5V			0.75		LSB
		ADC clock = 50 - 200 kHz
	Integral Non-Linearity (INL)
		Gain = 10x
	(Accuracy after Calibration for Offset and	VREF = 4V, VCC = 5V			0.75		LSB
	Gain Error)	ADC clock = 50 - 200 kHz
		Gain = 200x
		VREF = 4V, VCC = 5V			3.5		LSB
		ADC clock = 50 - 200 kHz
		Gain =	1x		1.7		%
	Gain Error	Gain =	10x		1.6		%
		Gain = 200x			0.3		%
		Gain = 1x
		VREF = 4V, VCC = 5V			2		LSB
		ADC clock = 50 - 200 kHz
		Gain = 10x
	Offset Error	VREF = 4V, VCC = 5V			2.5		LSB
		ADC clock = 50 - 200 kHz
		Gain = 200x
		VREF = 4V, VCC = 5V			3.5		LSB
		ADC clock = 50 - 200 kHz
	Clock Frequency			50		200	kHz
	Conversion Time			65		260	µs
AVCC	Analog Supply Voltage			VCC - 0.3(2)		VCC + 0.3(3)	V
VREF	Reference Voltage			2.0		AVCC- 0.5	V
VIN	Input Voltage			GND		VCC	V
VDIFF	Input Differential Voltage			-VREF/Gain		VREF/Gain	V
	ADC Conversion Output			-511		511	LSB
	Input Bandwidth				4		kHz

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Table 115. ADC Characteristics, Differential Channels (Continued)

Symbol	Parameter	Condition	Min(1)	Typ(1)	Max(1)	Units
VINT	Internal Voltage Reference		2.3	2.56	2.7	V
RREF	Reference Input Resistance			32		kΩ
RAIN	Analog Input Resistance			100		MΩ

Notes: 1. Values are guidelines only.

2.Minimum for AVCC is 2.7V.

3.Maximum for AVCC is 5.5V.

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