Differential Gain Channels

Changing Channel or Reference Selection

2502F–AVR–06/04

ATmega8535(L)

Table 82. ADC Conversion Time

	Sample & Hold (Cycles	Conversion Time
Condition	from Start of Conversion)	(Cycles)
First conversion	14.5	25
Normal conversions, single ended	1.5	13
Auto Triggered conversions	2	13.5
Normal conversions, differential	1.5/2.5(1)	13/14(1)

Note: 1. Depending on the state of CKADC2.

When using differential gain channels, certain aspects of the conversion need to be taken into consideration.

Differential conversions are synchronized to the internal clock CKADC2 equal to half the ADC clock. This synchronization is done automatically by the ADC interface in such a

way that the sample-and-hold occurs at a specific phase of CKADC2. A conversion initiated by the user (i.e., all single conversions, and the first free running conversion) when

CKADC2 is low will take the same amount of time as a single ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A conversion initiated by the user

when CKADC2 is high will take 14 ADC clock cycles due to the synchronization mechanism. In free running mode, a new conversion is initiated immediately after the previous

conversion completes, and since CKADC2 is high at this time, all automatically started (i.e., all but the first) free running conversions will take 14 ADC clock cycles.

The gain stage is optimized for a bandwidth of 4 kHz at all gain settings. Higher frequencies may be subjected to non-linear amplification. An external low-pass filter should be used if the input signal contains higher frequency components than the gain stage bandwidth. Note that the ADC clock frequency is independent of the gain stage bandwidth limitation. For example, the ADC clock period may be 6 µs, allowing a channel to be sampled at 12 kSPS, regardless of the bandwidth of this channel.

If differential gain channels are used and conversions are started by Auto Triggering, the ADC must be switched off between conversions. When Auto Triggering is used, the ADC prescaler is reset before the conversion is started. Since the gain stage is dependent of a stable ADC clock prior to the conversion, this conversion will not be valid. By disabling and then re-enabling the ADC between each conversion (writing ADEN in ADCSRA to “0” then to “1”), only extended conversions are performed. The result from the extended conversions will be valid. See “Prescaling and Conversion Timing” on page 206 for timing details.

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written.

If Auto Triggering is used, the exact time of the triggering event can be indeterminable. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings.

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	If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If
	the ADMUX Register is changed in this period, the user cannot tell if the next conversion
	is based on the old or the new settings. ADMUX can be safely updated in the following
	ways:
	1. When ADATE or ADEN is cleared.
	2. During conversion, minimum one ADC clock cycle after the trigger event.
	3. After a conversion, before the interrupt flag used as trigger source is cleared.
	When updating ADMUX in one of these conditions, the new settings will affect the next
	ADC conversion.
	Special care should be taken when changing differential channels. Once a differential
	channel has been selected, the gain stage may take as much as 125 µs to stabilize to
	the new value. Thus conversions should not be started within the first 125 µs after
	selecting a new differential channel. Alternatively, conversion results obtained within this
	period should be discarded.
	The same settling time should be observed for the first differential conversion after
	changing ADC reference (by changing the REFS1:0 bits in ADMUX).
ADC Input Channels	When changing channel selections, the user should observe the following guidelines to
	ensure that the correct channel is selected:
	In Single Conversion mode, always select the channel before starting the conversion.
	The channel selection may be changed one ADC clock cycle after writing one to ADSC.
	However, the simplest method is to wait for the conversion to complete before changing
	the channel selection.
	In Free Running mode, always select the channel before starting the first conversion.
	The channel selection may be changed one ADC clock cycle after writing one to ADSC.
	However, the simplest method is to wait for the first conversion to complete, and then
	change the channel selection. Since the next conversion has already started automati-
	cally, the next result will reflect the previous channel selection. Subsequent conversions
	will reflect the new channel selection.
	When switching to a differential gain channel, the first conversion result may have a
	poor accuracy due to the required settling time for the automatic offset cancellation cir-
	cuitry. The user should preferably disregard the first conversion result.
ADC Voltage Reference	The reference voltage for the ADC (VREF) indicates the conversion range for the ADC.
	Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be
	selected as either AVCC, internal 2.56V reference, or external AREF pin.
	AVCC is connected to the ADC through a passive switch. The internal 2.56V reference
	is generated from the internal bandgap reference (VBG) through an internal amplifier. In
	either case, the external AREF pin is directly connected to the ADC, and the reference
	voltage can be made more immune to noise by connecting a capacitor between the
	AREF pin and ground. VREF can also be measured at the AREF pin with a high impedant
	voltmeter. Note that VREF is a high impedant source, and only a capacitive load should
	be connected in a system.
	If the user has a fixed voltage source connected to the AREF pin, the user may not use
	the other reference voltage options in the application, as they will be shorted to the
	external voltage. If no external voltage is applied to the AREF pin, the user may switch
	between AVCC and 2.56V as reference selection. The first ADC conversion result after
	switching reference voltage source may be inaccurate, and the user is advised to dis-
	card this result.

210 ATmega8535(L)

2502F–AVR–06/04