- •Features
- •Pin Configurations
- •Disclaimer
- •Overview
- •Block Diagram
- •AT90S8535 Compatibility
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog-to-Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •SS Pin Functionality
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •SCL and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •Boot Loader Features
- •Application Section
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •Active Supply Current
- •Idle Supply Current
- •Power-Save Supply Current
- •Standby Supply Current
- •Pin Pullup
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega8535 all rev.
- •Datasheet Change Log for ATmega8535
- •Changes from Rev. 2502E-12/03 to Rev. 2502F-06/04
- •Changes from Rev. 2502D-09/03 to Rev. 2502E-12/03
- •Changes from Rev. 2502C-04/03 to Rev. 2502D-09/03
- •Changes from Rev. 2502B-09/02 to Rev. 2502C-04/03
- •Changes from Rev. 2502A-06/02 to Rev. 2502B-09/02
- •Table of Contents
Serial Downloading
Serial Programming Pin
Mapping
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input), and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 107 on page 248, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface.
Table 107. Pin Mapping Serial Programming
Symbol |
Pins |
I/O |
Description |
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MOSI |
PB5 |
I |
Serial Data in |
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MISO |
PB6 |
O |
Serial Data out |
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SCK |
PB7 |
I |
Serial Clock |
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Figure 124. Serial Programming and Verify(1)
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2.7 - 5.5V |
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VCC |
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2.7 - 5.5V(2) |
MOSI |
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PB5 |
AVCC |
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MISO |
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PB6 |
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SCK |
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PB7 |
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XTAL1 |
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RESET
GND
Notes: 1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the XTAL1 pin.
2. VCC - 0.3 < AVCC < VCC + 0.3. However, AVCC should always be within 2.7 - 5.5V.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows:
Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz
248 ATmega8535(L)
2502F–AVR–06/04
Serial Programming
Algorithm
Data Polling Flash
2502F–AVR–06/04
ATmega8535(L)
When writing serial data to the ATmega8535, data is clocked on the rising edge of SCK.
When reading data from the ATmega8535, data is clocked on the falling edge of SCK. See Figure 125 for timing details.
To program and verify the ATmega8535 in the Serial Programming mode, the following sequence is recommended (See four byte instruction formats in Table 109):
1.Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during Power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.
2.Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI.
3.The serial programming instructions will not work if the communication is out of synchronization. When in synchronization the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command.
4.The Flash is programmed one page at a time. The page size is found in Table 104 on page 238. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 8 MSB of the address. If polling is not used, the user must wait at least
tWD_FLASH before issuing the next page. (See Table 108.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming.
5.The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not
used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 108). In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
6.Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO.
7.At the end of the programming session, RESET can be set high to commence normal operation.
8.Power-off sequence (if needed): Set RESET to “1”.
Turn VCC power off.
When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value 0xFF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value 0xFF, so when programming this value, the user will have to wait for at
least tWD_FLASH before programming the next page. As a chip erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be
skipped. See Table 108 for tWD_FLASH value.
249
Data Polling EEPROM |
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When a new byte has been written and is being programmed into EEPROM, reading the |
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address location being programmed will give the value 0xFF. At the time the device is |
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ready for a new byte, the programmed value will read correctly. This is used to deter- |
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mine when the next byte can be written. This will not work for the value 0xFF, but the |
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user should have the following in mind: As a chip erased device contains 0xFF in all |
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locations, programming of addresses that are meant to contain 0xFF, can be skipped. |
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This does not apply if the EEPROM is reprogrammed without chip erasing the device. In |
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this case, data polling cannot be used for the value 0xFF, and the user will have to wait |
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at least tWD_EEPROM before programming the next byte. See Table 108 for tWD_EEPROM |
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value. |
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Table 108. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location |
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Minimum Wait Delay |
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tWD_FLASH |
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4.5 ms |
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tWD_EEPROM |
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9.0 ms |
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tWD_ERASE |
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9.0 ms |
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tWD_FUSE |
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4.5 ms |
Figure 125. Serial Programming Waveforms
SERIAL DATA INPUT |
MSB |
LSB |
(MOSI) |
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SERIAL DATA OUTPUT |
MSB |
LSB |
(MISO) |
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SERIAL CLOCK INPUT |
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(SCK) |
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SAMPLE |
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250 ATmega8535(L)
2502F–AVR–06/04
ATmega8535(L)
Table 109. Serial Programming Instruction Set
a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care
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Instruction Format |
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Instruction |
Byte 1 |
Byte 2 |
Byte 3 |
Byte4 |
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Operation |
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Programming Enable |
1010 1100 |
0101 0011 |
xxxx xxxx |
xxxx xxxx |
Enable Serial Programming after |
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RESET goes low. |
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Chip Erase |
1010 1100 |
100x xxxx |
xxxx xxxx |
xxxx xxxx |
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Chip Erase EEPROM and Flash. |
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0010 H000 |
0000 aaaa |
bbbb bbbb |
oooo oooo |
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Read H (high or low) data o from |
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Read Program Memory |
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Program memory at word address |
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a:b. |
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0100 H000 |
0000 xxxx |
xxxb bbbb |
iiii iiii |
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Write H (high or low) data i to |
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Load Program Memory |
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Program Memory page at word |
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address b. Data low byte must be |
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loaded before Data high byte is |
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applied within the same address. |
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Write Program Memory |
0100 1100 |
0000 aaaa |
bbbx xxxx |
xxxx xxxx |
Write Program Memory Page at |
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Page |
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address a:b. |
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Read EEPROM Memory |
1010 0000 |
00xx xxxa |
bbbb bbbb |
oooo oooo |
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Read data o from EEPROM |
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memory at address a:b. |
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Write EEPROM Memory |
1100 0000 |
00xx xxxa |
bbbb bbbb |
iiii iiii |
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Write data i to EEPROM memory |
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at address a:b. |
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0101 1000 |
0000 0000 |
xxxx xxxx |
xxoo oooo |
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Read Lock bits. “0” = programmed, |
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Read Lock Bits |
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“1” = unprogrammed. See Table |
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96 on page 234 for details. |
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1010 1100 |
111x xxxx |
xxxx xxxx |
11ii iiii |
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Write Lock bits. Set bits = “0” to |
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Write Lock Bits |
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program Lock bits. See Table 96 |
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on page 234 for details. |
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Read Signature Byte |
0011 0000 |
00xx xxxx |
xxxx xxbb |
oooo oooo |
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Read Signature Byte o at address |
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b. |
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1010 1100 |
1010 0000 |
xxxx xxxx |
iiii iiii |
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Set bits = “0” to program, “1” to |
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Write Fuse Bits |
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unprogram. See Table 99 on |
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page 236 for details. |
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1010 1100 |
1010 1000 |
xxxx xxxx |
iiii iiii |
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Set bits = “0” to program, “1” to |
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Write Fuse High Bits |
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unprogram. See Table 98 on |
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page 235 for details. |
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0101 0000 |
0000 0000 |
xxxx xxxx |
oooo oooo |
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Read Fuse bits. “0” = programmed, |
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Read Fuse Bits |
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“1” = unprogrammed. See Table |
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99 on page 236 for details. |
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0101 1000 |
0000 1000 |
xxxx xxxx |
oooo oooo |
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Read Fuse high bits. “0” = pro- |
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Read Fuse High Bits |
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grammed, “1” = unprogrammed. |
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See Table 98 on page 235 for |
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details. |
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Read Calibration Byte |
0011 1000 |
00xx xxxx |
0000 00bb |
oooo oooo |
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Read Calibration Byte |
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SPI Serial Programming |
For characteristics of the SPI module, see “SPI Timing Characteristics” on page 258. |
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Characteristics |
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251
2502F–AVR–06/04