ATmega8535(L)

Table 86. ADC Prescaler Selections

ADPS2	ADPS1	ADPS0	Division Factor
0	0	0	2
0	0	1	2
0	1	0	4
0	1	1	8
1	0	0	16
1	0	1	32
1	1	0	64
1	1	1	128

The ADC Data Register –

ADCL and ADCH

ADLAR = 0

Bit	15	14	13	12	11	10	9	8
	–	–	–	–	–	–	ADC9	ADC8	ADCH
	ADC7	ADC6	ADC5	ADC4	ADC3	ADC2	ADC1	ADC0	ADCL
	7	6	5	4	3	2	1	0
Read/Write	R	R	R	R	R	R	R	R
	R	R	R	R	R	R	R	R
Initial Value	0	0	0	0	0	0	0	0
	0	0	0	0	0	0	0	0

ADLAR = 1

Bit	15	14	13	12	11	10	9	8
	ADC9	ADC8	ADC7	ADC6	ADC5	ADC4	ADC3	ADC2	ADCH
	ADC1	ADC0	–	–	–	–	–	–	ADCL
	7	6	5	4	3	2	1	0
Read/Write	R	R	R	R	R	R	R	R
	R	R	R	R	R	R	R	R
Initial Value	0	0	0	0	0	0	0	0
	0	0	0	0	0	0	0	0

When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion

Result” on page 215.

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Special Function IO Register –

SFIOR

Bit	7	6		5				4	3	2	1	0
	ADTS2	ADTS1		ADTS0				–	ACME	PUD	PSR2	PSR10	SFIOR
Read/Write	R/W	R/W			R/W			R	R/W	R/W	R/W	R/W
Initial Value	0	0		0				0	0	0	0	0

• Bit 7:5 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected interrupt flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.

Table 87. ADC Auto Trigger Source Selections

ADTS2	ADTS1	ADTS0	Trigger Source
0	0	0	Free Running mode
0	0	1	Analog Comparator
0	1	0	External Interrupt Request 0
0	1	1	Timer/Counter0 Compare Match
1	0	0	Timer/Counter0 Overflow
1	0	1	Timer/Counter1 Compare Match B
1	1	0	Timer/Counter1 Overflow
1	1	1	Timer/Counter1 Capture Event

• Bit 4 – RES: Reserved Bit

This bit is reserved bit in the ATmega8535, and will always read as zero.

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ATmega8535(L)

Boot Loader Support

– Read-While-Write

Self-Programming

The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resi- dent Boot Loader program. The Boot Loader program can use any available data interface and associated protocol to read code and write (program) that code into the Flash memory, or read the code from the Program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection.

Boot Loader Features

•Read-While-Write Self-Programming

•Flexible Boot Memory Size

•High Security (Separate Boot Lock Bits for a Flexible Protection)

•Separate Fuse to Select Reset Vector

•Optimized Page(1) Size

•Code Efficient Algorithm

•Efficient Read-Modify-Write Support

Note: 1. A page is a section in the Flash consisting of several bytes (see Table 104 on page 238) used during programming. The page organization does not affect normal operation.

Application and Boot

Loader Flash Sections

Application Section

The Flash memory is organized in two main sections, the Application section and the Boot Loader section (see Figure 113). The size of the different sections is configured by the BOOTSZ Fuses as shown in Table 93 on page 232 and Figure 113. These two sections can have different level of protection since they have different sets of Lock bits.

The Application section is the section of the Flash that is used for storing the application code. The protection level for the Application section can be selected by the Application Boot Lock bits (Boot Lock bits 0), see Table 89 on page 224. The Application section can never store any Boot Loader code since the SPM instruction is disabled when executed from the Application section.

BLS – Boot Loader Section While the Application section is used for storing the application code, the The Boot Loader software must be located in the BLS since the SPM instruction can initiate a programming when executing from the BLS only. The SPM instruction can access the entire Flash, including the BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader Lock bits (Boot Lock bits 1), see Table 90 on page 224.

Read-While-Write and No

Read-While-Write Flash

Sections

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Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-Write (NRWW) section. The limit between the RWWand NRWW sections is given in Table 94 on page 232 and Figure 113 on page 223. The main difference between the two sections is:

•When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation.

•When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation.

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Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax “Read-While-Write Section” refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update.

RWW – Read-While-Write If a Boot Loader software update is programming a page inside the RWW section, it is Section possible to read code from the Flash, but only code that is located in the NRWW section. During an on-going programming, the software must ensure that the RWW section never is being read. If the user software is trying to read code that is located inside the RWW section (i.e., by a rcall/rjmp/lpm or an interrupt) during programming, the software might end up in an unknown state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader section. The Boot Loader section is always located in the NRWW section. The RWW Section Busy bit (RWWSB) in the Store Program Memory Control Register (SPMCR) will be read as logical one as long as the RWW section is blocked for reading. After a programming is completed, the RWWSB must be cleared by software before reading code located in the RWW section. See “Store Program Memory

Control Register – SPMCR” on page 225. for details on how to clear RWWSB.

NRWW – No Read-While-Write The code located in the NRWW section can be read when the Boot Loader software is Section updating a page in the RWW section. When the Boot Loader code updates the NRWW

section, the CPU is halted during the entire page erase or page write operation.

Table 88. Read-While-Write Features

Which Section does the Z-	Which Section can be	Is the	Read-While-
pointer Address During the	Read During	CPU	Write
Programming?	Programming?	Halted?	Supported?
RWW section	NRWW section	No	Yes
NRWW section	None	Yes	No

Figure 112. Read-While-Write vs. No Read-While-Write

Read-While-Write

(RWW) Section

	Z-pointer
	Addresses NRWW
Z-pointer	Section
Addresses RWW	No Read-While-Write
Section	(NRWW) Section
	CPU is Halted
Code Located in	During the Operation
NRWW Section
can be Read During
the Operation

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