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Lab2 / Литература / ATmega8535 DATA SHEET.pdf
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ATmega8535(L)

Timed Sequences for Changing the Configuration of the Watchdog Timer

The sequence for changing the Watchdog Timer configuration differs slightly between the three safety levels. Separate procedures are described for each level.

Safety Level 0

This mode is compatible with the Watchdog operation found in AT90S8535. The Watch-

 

dog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without

 

any restriction. The Time-out period can be changed at any time without restriction. To

 

disable an enabled Watchdog Timer and/or changing the Watchdog Time-out, the fol-

 

lowing procedure must be followed:

 

1.

In the same operation, write a logic one to WDCE and WDE. A logic one must be

 

 

written to WDE regardless of the previous value of the WDE bit.

 

2.

Within the next four clock cycles, in the same operation, write the WDE and WDP

 

 

bits as desired, but with the WDCE bit cleared.

Safety Level 1

In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the

 

WDE bit to 1 without any restriction. A timed sequence is needed when changing the

 

Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an

 

enabled Watchdog Timer and/or changing the Watchdog Time-out, the following proce-

 

dure must be followed:

 

1.

In the same operation, write a logic one to WDCE and WDE. A logic one must be

 

 

written to WDE regardless of the previous value of the WDE bit.

 

2.

Within the next four clock cycles, in the same operation, write the WDE and WDP

 

 

bits as desired, but with the WDCE bit cleared.

Safety Level 2

In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read

 

as one. A timed sequence is needed when changing the Watchdog Time-out period. To

 

change the Watchdog Time-out, the following procedure must be followed:

 

1.

In the same operation, write a logical one to WDCE and WDE. Even though the

 

 

WDE always is set, the WDE must be written to one to start the timed sequence.

 

2.

Within the next four clock cycles, in the same operation, write the WDP bits as

 

 

desired, but with the WDCE bit cleared. The value written to the WDE bit is

 

 

irrelevant.

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2502F–AVR–06/04