- •Features
- •Pin Configurations
- •Disclaimer
- •Overview
- •Block Diagram
- •AT90S8535 Compatibility
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog-to-Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •SS Pin Functionality
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •SCL and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •Boot Loader Features
- •Application Section
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •Active Supply Current
- •Idle Supply Current
- •Power-Save Supply Current
- •Standby Supply Current
- •Pin Pullup
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega8535 all rev.
- •Datasheet Change Log for ATmega8535
- •Changes from Rev. 2502E-12/03 to Rev. 2502F-06/04
- •Changes from Rev. 2502D-09/03 to Rev. 2502E-12/03
- •Changes from Rev. 2502C-04/03 to Rev. 2502D-09/03
- •Changes from Rev. 2502B-09/02 to Rev. 2502C-04/03
- •Changes from Rev. 2502A-06/02 to Rev. 2502B-09/02
- •Table of Contents
Electrical Characteristics
Absolute Maximum Ratings*
..................................Operating Temperature |
-55°C to +125°C |
*NOTICE: Stresses beyond those listed under “Absolute |
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Maximum Ratings” may cause permanent dam- |
Storage Temperature ..................................... |
-65°C to +150°C |
age to the device. This is a stress rating only and |
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functional operation of the device at these or |
Voltage on any Pin except |
RESET |
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other conditions beyond those indicated in the |
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with respect to Ground ................................ |
- 0.5V to VCC+0.5V |
operational sections of this specification is not |
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Voltage on |
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with respect to Ground |
-0.5V to +13.0V |
implied. Exposure to absolute maximum rating |
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RESET |
conditions for extended periods may affect device |
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Maximum Operating Voltage |
6.0V |
reliability. |
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DC Current per I/O Pin ............................................... |
40.0 mA |
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DC Current VCC and GND Pins ................................ |
200.0 mA |
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DC Characteristics
TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted)
Symbol |
Parameter |
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Condition |
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Min |
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Typ |
Max |
Units |
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VIL |
Input Low Voltage |
Except XTAL1 pin |
-0.5 |
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(1) |
V |
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0.2 VCC |
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XTAL1 pin, External |
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(1) |
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VIL1 |
Input Low Voltage |
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Clock Selected |
-0.5 |
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0.1 VCC |
V |
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VIH |
Input High Voltage |
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Except XTAL1 and |
0.6 VCC |
(2) |
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VCC |
+ 0.5 |
V |
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RESET |
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VIH1 |
Input High Voltage |
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XTAL1 pin, External |
0.8 VCC |
(2) |
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VCC |
+ 0.5 |
V |
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Clock Selected |
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(2) |
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VIH2 |
Input High Voltage |
RESET pin |
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0.9 VCC |
VCC |
+ 0.5 |
V |
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Output Low Voltage(3) |
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I |
OL |
= 20 mA, V |
= 5V |
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0.7 |
V |
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VOL |
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CC |
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(Ports A,B,C,D) |
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IOL = 10 mA, VCC = 3V |
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0.5 |
V |
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VOH |
Output High Voltage(4) |
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IOH = -20 mA, VCC = 5V |
4.2 |
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V |
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(Ports A,B,C,D) |
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IOH = -10 mA, VCC = 3V |
2.2 |
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V |
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IIL |
Input Leakage |
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VCC = 5.5V, pin low |
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1 |
µA |
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Current I/O Pin |
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(absolute value) |
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IIH |
Input Leakage |
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VCC = 5.5V, pin high |
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1 |
µA |
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Current I/O Pin |
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(absolute value) |
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RRST |
Reset Pull-up Resistor |
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30 |
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60 |
kΩ |
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Rpu |
I/O Pin Pull-up Resistor |
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20 |
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50 |
kΩ |
252 ATmega8535(L)
2502F–AVR–06/04
ATmega8535(L)
TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted) |
(Continued) |
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Symbol |
Parameter |
Condition |
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Min |
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Max |
Units |
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Active 4 MHz, VCC = 3V |
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4 |
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mA |
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(ATmega8535L) |
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Active 8 MHz, VCC = 5V |
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14 |
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mA |
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(ATmega8535) |
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Power Supply Current |
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ICC |
Idle 4 MHz, VCC = 3V |
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3 |
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mA |
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Idle 8 MHz, VCC = 5V |
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10 |
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mA |
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(ATmega8535) |
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Power-down mode(5) |
WDT enabled, VCC = 3V |
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< 10 |
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µA |
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WDT disabled, VCC = 3V |
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< 3 |
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µA |
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VACIO |
Analog Comparator |
VCC = 5V |
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40 |
mV |
Input Offset Voltage |
Vin = VCC/2 |
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IACLK |
Analog Comparator |
VCC = 5V |
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-50 |
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50 |
nA |
Input Leakage Current |
Vin = VCC/2 |
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tACID |
Analog Comparator |
VCC = 2.7V |
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750 |
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Propagation Delay |
VCC = 4.0V |
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500 |
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Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.
2.“Min” means the lowest value where the pin is guaranteed to be read as high.
3.Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed:
PDIP Package:
1] The sum of all IOL, for all ports, should not exceed 200 mA.
2] The sum of all IOL, for port A0 - A7, should not exceed 100 mA.
3] The sum of all IOL, for ports B0 - B7,C0 - C7, D0 - D7 and XTAL2, should not exceed 100 mA. TQFP Package:
1] The sum of all IOL, for all ports, should not exceed 400 mA.
2] The sum of all IOL, for ports A0 - A7, should not exceed 100 mA. 3] The sum of all IOL, for ports B0 - B3, should not exceed 100 mA. 4] The sum of all IOL, for ports B4 - B7, should not exceed 100 mA. 5] The sum of all IOL, for ports C0 - C3, should not exceed 100 mA. 6] The sum of all IOL, for ports C4 - C7, should not exceed 100 mA.
7] The sum of all IOL, for ports D0 - D3 and XTAL2, should not exceed 100 mA. 8] The sum of all IOL, for ports D4 - D7, should not exceed 100 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.
4.Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed:
PDIP Package:
1] The sum of all IOH, for all ports, should not exceed 200 mA.
2] The sum of all IOH, for port A0 - A7, should not exceed 100 mA.
3] The sum of all IOH, for ports B0 - B7,C0 - C7, D0 - D7 and XTAL2, should not exceed 100 mA. TQFP Package:
1] The sum of all IOH, for all ports, should not exceed 400 mA.
2] The sum of all IOH, for ports A0 - A7, should not exceed 100 mA. 3] The sum of all IOH, for ports B0 - B3, should not exceed 100 mA. 4] The sum of all IOH, for ports B4 - B7, should not exceed 100 mA. 5] The sum of all IOH, for ports C0 - C3, should not exceed 100 mA. 6] The sum of all IOH, for ports C4 - C7, should not exceed 100 mA.
7] The sum of all IOH, for ports D0 - D3 and XTAL2, should not exceed 100 mA. 8] The sum of all IOH, for ports D4 - D7, should not exceed 100 mA
253
2502F–AVR–06/04
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.
5. Minimum VCC for Power-down is 2.5V.
254 ATmega8535(L)
2502F–AVR–06/04
ATmega8535(L)
External Clock Drive
Waveforms
External Clock Drive
Figure 126. External Clock Drive Waveforms
VIH1
VIL1
Table 110. External Clock Drive
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VCC = 2.7V to 5.5V |
VCC = 4.5V to 5.5V |
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Symbol |
Parameter |
Min |
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Max |
Min |
Max |
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Units |
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1/tCLCL |
Oscillator Frequency |
0 |
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8 |
0 |
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16 |
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MHz |
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tCLCL |
Clock Period |
125 |
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62.5 |
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tCHCX |
High Time |
50 |
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25 |
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tCLCX |
Low Time |
50 |
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25 |
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tCLCH |
Rise Time |
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1.6 |
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0.5 |
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µs |
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tCHCL |
Fall Time |
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1.6 |
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0.5 |
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µs |
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Change in period from |
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∆tCLCL |
one clock cycle to the |
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2 |
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2 |
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% |
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next |
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Table 111. External RC Oscillator, Typical Frequencies |
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R [kΩ](1) |
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C [pF] |
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f(2) |
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100 |
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47 |
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87 kHz |
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33 |
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22 |
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650 kHz |
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10 |
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22 |
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2.0 MHz |
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Notes: 1. R should be in the range 3 kΩ - 100 kΩ, and C should be at least 20 pF. The C values given in the table includes pin capacitance. This will vary with package type.
2. The frequency will vary with package type and board layout.
255
2502F–AVR–06/04