Fast page mode dram

All types of memory are addressed as an array of rows and columns, and individual bits are stored in each cell of the array. With standard DRAM or FPM DRAM, which comes with access times of 70ns or 60ns, the memory management unit reads data by first activating the appropriate row of the array, activating the correct column, validating the data and transferring the data back to the system. The column is then deactivated, which introduces an unwanted wait state where the processor has to wait for the memory to finish the transfer. The output data buffer is then turned off, ready for the next memory access.

At best, with this scheme FPM can achieve a burst rate timing as fast as 5-3-3-3. This means that reading the first element of data takes five clock cycles, containing four wait-states, with the next three elements each taking three.

DRAM speed improvements have historically come from process and photolithography advances. More recent improvements in performance however have resulted from changes to the base DRAM architecture that require little or no increase in die size. Extended Data Out (EDO) memory is an example of this.

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Extended data out dram

EDO memory comes in 70ns, 60ns and 50ns speeds. 60ns is the slowest that should be used in a 66MHz bus speed system (i.e. Pentium 100MHz and above) and the Triton HX and VX chipsets can also take advantage of the 50ns version. EDO DRAM doesn't demand that the column be deactivated and the output buffer turned off before the next data transfer starts. It therefore achieves a typical burst timing of 5-2-2-2 at a bus speed of 66MHz and can complete some memory reads a theoretical 27% faster than FPM DRAM.

Burst Extended Data Out dram

Burst EDO DRAM is an evolutionary improvement in EDO DRAM that contains a pipeline stage and a 2-bit burst counter. With the conventional DRAMs such as FPM and EDO, the initiator accesses DRAM through a memory controller. The controller must wait for the data to become ready before sending it to the initiator. BEDO eliminates the wait-states thus improving system performance by up to 100% over FPM DRAM and up to 50% over standard EDO DRAM, achieving system timings of 5-1-1-1 when used with a supporting chipset.

Despite the fact that BEDO arguably provides more improvement over EDO than EDO does over FPM the standard has lacked chipset support and has consequently never really caught on, losing out to Synchronous DRAM (SDRAM).

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SDRAM

The more recent Synchronous DRAM memory works quite differently from other memory types. It exploits the fact that most PC memory accesses are sequential and is designed to fetch all the bits in a burst as fast as possible. With SDRAM an on-chip burst counter allows the column part of the address to be incremented very rapidly which helps speed up retrieval of information in sequential reads considerably. The memory controller provides the location and size of the block of memory required and the SDRAM chip supplies the bits as fast as the CPU can take them, using a clock to synchronise the timing of the memory chip to the CPU's system clock.

This key feature of SDRAM gives it an important advantage over other, asynchronous memory types, enabling data to be delivered off-chip at burst rates of up to 100MHz. Once the burst has started all remaining bits of the burst length are delivered at a 10ns rate. At a bus speed of 66MHz SDRAMs can reduce burst rates to 5/1/1/1. The first figure is higher than the timings for FPM and EDO RAM because more setting up is required for the initial data transfer. Even so, there's a theoretical improvement of 18% over EDO for the right type of data transfers.

However, since no reduction in the initial access is gained, it was not until the release of Intel's 440BX chipset, in early 1998, that the benefit of 100MHz page cycle time was fully exploited. However, even SDRAM cannot be considered as anything more than a stop-gap product as the matrix interconnection topology of the legacy architecture of SDRAM makes it difficult to move to frequencies much beyond 100MHz. The legacy pin function definition - separate address, control and data/DQM lines - controlled by the same clock source leads to a complex board layout with difficult timing margin issues. The 100MHz layout and timing issues might be addressed by skilful design, but only through the addition of buffering registers, which increases lead-off latency and adds to power dissipation and system cost.

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