Figure 93. Formats and States in the Slave Transmitter Mode

Reception of the own

S

SLA

R

A

DATA

A

DATA

P or S

slave address and one or

A

more data bytes

$A8

$B8

$C0

Arbitration lost as master

A

and addressed as slave

$B0

Last data byte transmitted.

A

All 1's

P or S

Switched to not addressed

slave (TWEA = '0')

$C8

Any number of data bytes

From master to slave

DATA

A

and their associated acknowledge bits

From slave to master

n

This number (contained in TWSR) corresponds

to a defined state of the Two-wire Serial Bus. The

prescaler bits are zero or masked to zero

Miscellaneous States There are two status codes that do not correspond to a defined TWI state, see Table 78.

Status $F8 indicates that no relevant information is available because the TWINT Flag is not set.

This occurs between other states, and when the TWI is not involved in a serial transfer.

Status $00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in TWCR are affected). The SDA and SCL lines are released, and no STOP condition is transmitted.

Table 78.	Miscellaneous States
Status Code			Application Software Response
(TWSR)		Status of the Two-wire Serial			To TWCR
Prescaler Bits		Bus and Two-wire Serial Inter-
			To/from TWDR	STA	STO	TWINT	TWEA	Next Action Taken by TWI Hardware
are 0		face Hardware
$F8		No relevant state information	No TWDR action		No TWCR action			Wait or proceed current transfer
		available; TWINT = “0”
$00		Bus error due to an illegal	No TWDR action	0	1	1	X	Only the internal hardware is affected, no STOP condi-
		START or STOP condition						tion is sent on the bus. In all cases, the bus is released
								and TWSTO is cleared.

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ATmega16(L)

Combining Several

TWI Modes

Multi-master

Systems and

Arbitration

In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps:

1.The transfer must be initiated

2.The EEPROM must be instructed what location should be read

3.The reading must be performed

4.The transfer must be finished

Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The Master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation. If this principle is violated in a multi-master system, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the Master will read the wrong data location. Such a change in transfer direction is accomplished by transmitting a REPEATED START between the transmission of the address byte and reception of the data. After a REPEATED START, the Master keeps ownership of the bus. The following figure shows the flow in this transfer.

Figure 94. Combining Several TWI Modes to Access a Serial EEPROM

Master Transmitter

Master Receiver

S

SLA+W

A

ADDRESS

A

Rs

SLA+R

A

DATA

A

P

S = START

Rs = REPEATED START

P = STOP

Transmitted from Master to Slave

Transmitted from Slave to Master

If multiple Masters are connected to the same bus, transmissions may be initiated simultaneously by one or more of them. The TWI standard ensures that such situations are handled in such a way that one of the Masters will be allowed to proceed with the transfer, and that no data will be lost in the process. An example of an arbitration situation is depicted below, where two Masters are trying to transmit data to a Slave Receiver.

Figure 95. An Arbitration Example

VCC

Device 1

Device 2

Device 3

........

Device n

R1

R2

MASTER

MASTER

SLAVE

TRANSMITTER

TRANSMITTER

RECEIVER

SDA

SCL

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Several different scenarios may arise during arbitration, as described below:

•Two or more Masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the Masters will know about the bus contention.

•Two or more Masters are accessing the same Slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The Masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration. Losing Masters will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition, depending on application software action.

•Two or more Masters are accessing different Slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning Master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit. If they are not being addressed, they will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition, depending on application software action.

This is summarized in Figure 96. Possible status values are given in circles.

Figure 96. Possible Status Codes Caused by Arbitration

START		SLA	Data	STOP
		Arbitration lost in SLA	Arbitration lost in Data

Own	No
Address / General Call
received

Yes

Write

Direction

Read

38
	TWI bus will be released and not addressed slave mode will be entered
	A START condition will be transmitted when the bus becomes free

68/78 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned

	Last data byte will be transmitted and NOT ACK should be received
B0	Data byte will be transmitted and ACK should be received

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ATmega16(L)

Analog

Comparator

The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 97.

Figure 97. Analog Comparator Block Diagram(2)

BANDGAP

REFERENCE

ACBG

ACME

ADEN

ADC MULTIPLEXER

OUTPUT (1)

Special Function IO

Register – SFIOR

Notes: 1. See Table 80 on page 203.

2. Refer to Figure 1 on page 2 and Table 25 on page 58 for Analog Comparator pin placement.

Bit	7	6	5	4	3	2	1	0
	ADTS2	ADTS1	ADTS0	–	ACME	PUD	PSR2	PSR10	SFIOR
Read/Write	R/W	R/W	R/W	R	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

• Bit 3 – ACME: Analog Comparator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 203.

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Analog Comparator

Control and Status

Register – ACSR

Bit	7	6	5	4					3	2	1	0
	ACD	ACBG	ACO			ACI			ACIE	ACIC	ACIS1	ACIS0	ACSR
Read/Write	R/W	R/W	R			R/W			R/W	R/W	R/W	R/W
Initial Value	0	0	N/A	0					0	0	0	0

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator Interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set.

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 79.

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