- •Features
- •Disclaimer
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •Resources
- •Data Retention
- •AVR CPU Core
- •Introduction
- •Status Register
- •Stack Pointer
- •I/O Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Watchdog Reset
- •Watchdog Timer
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Register Description for I/O Ports
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Timer/Counter0 and Timer/Counter1 Prescalers
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Noise Canceler
- •Force Output Compare
- •Normal Mode
- •Fast PWM Mode
- •16-bit Timer/Counter Register Description
- •8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Frame Formats
- •Parity Bit Calculation
- •Parity Generator
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Using MPCM
- •Write Access
- •Read Access
- •Features
- •TWI Terminology
- •Transferring Bits
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •SCL and SDA Pins
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •Using the TWI
- •Master Receiver Mode
- •Slave Receiver Mode
- •Miscellaneous States
- •Analog Comparator Multiplexed Input
- •Analog to Digital Converter
- •Features
- •Operation
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •Analog Input Circuitry
- •Features
- •Overview
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •IEEE 1149.1 (JTAG) Boundary-scan
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Reset Register
- •EXTEST; $0
- •IDCODE; $1
- •AVR_RESET; $C
- •BYPASS; $F
- •Scanning the ADC
- •ATmega16 Boundary-scan Order
- •Features
- •Application Section
- •Read-While-Write and no Read- While-Write Flash Sections
- •Prevent Reading the RWW Section during Self-Programming
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Programming Command Register
- •Virtual Flash Page Read Register
- •Performing Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics
- •Idle Supply Current
- •Pin Pullup
- •Pin Driver Strength
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
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Table 104. |
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Lock Bit Protection Modes (Continued) |
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Memory Lock Bits(2) |
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Protection Type |
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1 |
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1 |
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1 |
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No restrictions for SPM or LPM accessing the Boot Loader |
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section. |
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2 |
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1 |
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0 |
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SPM is not allowed to write to the Boot Loader section. |
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SPM is not allowed to write to the Boot Loader section, |
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and LPM executing from the Application section is not |
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3 |
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0 |
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allowed to read from the Boot Loader section. If interrupt |
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vectors are placed in the Application section, interrupts |
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are disabled while executing from the Boot Loader section. |
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LPM executing from the Application section is not allowed |
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4 |
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0 |
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1 |
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to read from the Boot Loader section. If interrupt vectors |
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are placed in the Application section, interrupts are |
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disabled while executing from the Boot Loader section. |
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Notes: 1. Program the Fuse bits before programming the Lock bits. |
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2. “1” means unprogrammed, “0” means programmed |
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Fuse Bits |
The ATmega16 has two fuse bytes. Table 105 and Table 106 describe briefly the functionality of |
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all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logi- |
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cal zero, “0”, if they are programmed. |
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Table 105. Fuse High Byte |
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Fuse High |
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Bit |
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Byte |
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No. |
Description |
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Default Value |
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OCDEN(4) |
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7 |
Enable OCD |
1 (unprogrammed, OCD disabled) |
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JTAGEN(5) |
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6 |
Enable JTAG |
0 (programmed, JTAG enabled) |
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SPIEN(1) |
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5 |
Enable SPI Serial Program and |
0 (programmed, SPI prog. enabled) |
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Data Downloading |
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CKOPT(2) |
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4 |
Oscillator options |
1 (unprogrammed) |
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EESAVE |
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3 |
EEPROM memory is preserved |
1 (unprogrammed, EEPROM not |
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through the Chip Erase |
preserved) |
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BOOTSZ1 |
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2 |
Select Boot Size (see Table 100 |
0 (programmed)(3) |
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for details) |
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BOOTSZ0 |
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1 |
Select Boot Size (see Table 100 |
0 (programmed)(3) |
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for details) |
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BOOTRST |
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0 |
Select reset vector |
1 (unprogrammed) |
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Notes: 1. |
The SPIEN Fuse is not accessible in SPI Serial Programming mode. |
2.The CKOPT Fuse functionality depends on the setting of the CKSEL bits. See See “Clock Sources” on page 25. for details.
3.The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 100 on page 257.
4.Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits and the JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to be running in all sleep modes. This may increase the power consumption.
5.If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be disabled. This to avoid static current at the TDO pin in the JTAG interface.
260 ATmega16(L)
2466P–AVR–08/07