ATmega16(L)

Performing Page	To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCR and
Erase by SPM	execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored.
	The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer must
	be written zero during this operation.
	• Page Erase to the RWW section: The NRWW section can be read during the page erase.
	• Page Erase to the NRWW section: The CPU is halted during the operation.
Filling the Temporary	To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
Buffer (Page Loading)	“00000001” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The con-
	tent of PCWORD in the Z-register is used to address the data in the temporary buffer. The
	temporary buffer will auto-erase after a page write operation or by writing the RWWSRE bit in
	SPMCR. It is also erased after a system reset. Note that it is not possible to write more than one
	time to each address without erasing the temporary buffer.
	Note: If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be
	lost.

Performing a Page To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCR and Write execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE. Other bits in the Z-pointer must be written zero during this operation.

•Page Write to the RWW section: The NRWW section can be read during the Page Write.

•Page Write to the NRWW section: The CPU is halted during the operation.

Using the SPM	If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the
Interrupt	SPMEN bit in SPMCR is cleared. This means that the interrupt can be used instead of polling
	the SPMCR Register in software. When using the SPM interrupt, the Interrupt Vectors should be
	moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is
	blocked for reading. How to move the interrupts is described in “Interrupts” on page 45.
Consideration while	Special care must be taken if the user allows the Boot Loader section to be updated by leaving
Updating BLS	Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the
	entire Boot Loader, and further software updates might be impossible. If it is not necessary to
	change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to
	protect the Boot Loader software from any internal software changes.

Prevent Reading the RWW Section during Self-Programming

During Self-Programming (either Page Erase or Page Write), the RWW section is always blocked for reading. The user software itself must prevent that this section is addressed during the Self-Programming operation. The RWWSB in the SPMCR will be set as long as the RWW section is busy. During self-programming the Interrupt Vector table should be moved to the BLS as described in “Interrupts” on page 45, or the interrupts must be disabled. Before addressing the RWW section after the programming is completed, the user software must clear the RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on page 256 for an example.

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Setting the Boot
	To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCR and
Loader Lock Bits by	execute SPM within four clock cycles after writing SPMCR. The only accessible Lock bits are the
SPM	Boot Lock bits that may prevent the Application and Boot Loader section from any software
	update by the MCU.
	Bit	7	6	5	4				3	2	1	0
	R0
		1	1	BLB12			BLB11		BLB02	BLB01	1	1

See Table 96 and Table 97 for how the different settings of the Boot Loader bits affect the Flash access.

If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCR. The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to load the Z-pointer with $0001 (same as used for reading the Lock bits). For future compatibility It is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock bits. When programming the Lock bits the entire Flash can be read during the operation.

EEPROM Write	Note that an EEPROM write operation will block all software programming to Flash. Reading the
Prevents Writing to	Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
SPMCR	is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies
	that the bit is cleared before writing to the SPMCR Register.
Reading the Fuse and	It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Lock Bits from	Z-pointer with $0001 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruction
Software	is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCR, the
	value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN bits
	will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed
	within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB-
	SET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
	Bit		7	6	5	4	3	2	1	0
	Rd
			–	–	BLB12	BLB11	BLB02	BLB01	LB2	LB1

The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock bits. To read the Fuse Low bits, load the Z-pointer with $0000 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to Table 106 on page 261 for a detailed description and mapping of the Fuse Low bits.

Bit	7	6	5	4	3	2	1	0
Rd	FLB7	FLB6	FLB5	FLB4	FLB3	FLB2	FLB1	FLB0

Similarly, when reading the Fuse High bits, load $0003 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the Fuse High bits (FHB) will be loaded in the destination register as shown below. Refer to Table 105 on page 260 for detailed description and mapping of the Fuse High bits.

	Bit	7	6	5	4	3	2	1	0
	Rd	FHB7	FHB6	FHB5	FHB4	FHB3	FHB2	FHB1	FHB0
	Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
	unprogrammed, will be read as one.
Preventing Flash	During periods of low VCC, the Flash program can be corrupted because the supply voltage is too
Corruption	low for the CPU and the Flash to operate properly. These issues are the same as for board level

systems using the Flash, and the same design solutions should be applied.

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A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low.

Flash corruption can easily be avoided by following these design recommendations (one is sufficient):

1.If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent any Boot Loader software updates.

2.Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-

age matches the detection level. If not, an external low VCC Reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

3.Keep the AVR core in Power-down Sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCR Register and thus the Flash from unintentional writes.

Programming Time for The Calibrated RC Oscillator is used to time Flash accesses. Table 99 shows the typical pro- Flash when using SPM gramming time for Flash accesses from the CPU.

Table 99. SPM Programming Time.

	Symbol	Min Programming Time	Max Programming Time
	Flash write (Page Erase, Page	3.7 ms	4.5 ms
	Write, and write Lock bits by SPM)

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temp1, SPMCR

Simple Assembly Code Example for a Boot Loader

;-the routine writes one page of data from RAM to Flash

;the first data location in RAM is pointed to by the Y pointer

;the first data location in Flash is pointed to by the Z pointer ;-error handling is not included

;-the routine must be placed inside the boot space

;(at least the Do_spm sub routine). Only code inside NRWW section can

;be read during self-programming (page erase and page write).

;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

;loophi (r25), spmcrval (r20)

;storing and restoring of registers is not included in the routine

;register usage can be optimized at the expense of code size

;-It is assumed that either the interrupt table is moved to the Boot ; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2		; PAGESIZEB is page size in BYTES, not
		; words
.org SMALLBOOTSTART
Write_page:
; page erase
ldi	spmcrval, (1<<PGERS) | (1<<SPMEN)
call	Do_spm
; re-enable the RWW section
ldi	spmcrval, (1<<RWWSRE) | (1<<SPMEN)
call	Do_spm
; transfer data from RAM to Flash page buffer
ldi	looplo, low(PAGESIZEB)	;init loop variable
ldi	loophi, high(PAGESIZEB)	;not required for PAGESIZEB<=256
Wrloop:
ld	r0, Y+
ld	r1, Y+
ldi	spmcrval, (1<<SPMEN)
call	Do_spm
adiw	ZH:ZL, 2
sbiw	loophi:looplo, 2	;use subi for PAGESIZEB<=256
brne	Wrloop
; execute page write
subi	ZL, low(PAGESIZEB)	;restore pointer
sbci	ZH, high(PAGESIZEB)	;not required for PAGESIZEB<=256
ldi	spmcrval, (1<<PGWRT) | (1<<SPMEN)
call	Do_spm
; re-enable the RWW section
ldi	spmcrval, (1<<RWWSRE) | (1<<SPMEN)
call	Do_spm
; read back and check, optional
ldi	looplo, low(PAGESIZEB)	;init loop variable
ldi	loophi, high(PAGESIZEB)	;not required for PAGESIZEB<=256
subi	YL, low(PAGESIZEB)	;restore pointer
sbci	YH, high(PAGESIZEB)
Rdloop:
lpm	r0, Z+
ld	r1, Y+
cpse	r0, r1
jmp	Error
sbiw	loophi:looplo, 1	;use subi for PAGESIZEB<=256
brne	Rdloop

;return to RWW section

;verify that RWW section is safe to read Return:

in

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sbrs temp1, RWWSB	;	If RWWSB is set, the RWW section is not
	;	ready yet

ret

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN) call Do_spm

rjmp Return

Do_spm:

; check for previous SPM complete Wait_spm:

in temp1, SPMCR sbrc temp1, SPMEN rjmp Wait_spm

;input: spmcrval determines SPM action

;disable interrupts if enabled, store status

in	temp2, SREG
cli

;check that no EEPROM write access is present Wait_ee:

sbic EECR, EEWE rjmp Wait_ee

;SPM timed sequence

out SPMCR, spmcrval spm

; restore SREG (to enable interrupts if originally enabled) out SREG, temp2

ret

ATmega16 Boot

In Table 100 through Table 102, the parameters used in the description of the self programming

Loader Parameters

are given.

Table 100. Boot Size Configuration(1)

Boot Reset

Boot

Address

Application

Loader

End

(start Boot

Boot

Flash

Flash

Application

Loader

BOOTSZ1

BOOTSZ0

Size

Pages

Section

Section

section

Section)

1

1

128

2

$0000 -

$1F80 -

$1F7F

$1F80

words

$1F7F

$1FFF

1

0

256

4

$0000 -

$1F00 -

$1EFF

$1F00

words

$1EFF

$1FFF

0

1

512

8

$0000 -

$1E00 -

$1DFF

$1E00

words

$1DFF

$1FFF

0

0

1024

16

$0000 -

$1C00 -

$1BFF

$1C00

words

$1BFF

$1FFF

Note: 1.

The different

BOOTSZ

Fuse

configurations are shown in Figure 125

Table 101. Read-While-Write Limit(1)

Section

Pages

Address

Read-While-Write section (RWW)

112

$0000 - $1BFF

No Read-While-Write section (NRWW)

16

$1C00 - $1FFF

Note: 1. For details about these two section, see “NRWW – No Read-While-Write Section” on page 247 and “RWW – Read-While-Write Section” on page 247

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Table 102. Explanation of Different Variables used in Figure 126 and the Mapping to the Z- pointer

			Corresponding
Variable			Z-value(1)		Description
PCMSB		12			Most significant bit in the Program Counter.
					(The Program Counter is 13 bits PC[12:0])
		5			Most significant bit which is used to address the
PAGEMSB					words within one page (64 words in a page
					requires 6 bits PC [5:0]).
			Z13		Bit in Z-register that is mapped to PCMSB.
ZPCMSB					Because Z0 is not used, the ZPCMSB equals
					PCMSB + 1.
			Z6		Bit in Z-register that is mapped to PAGEMSB.
ZPAGEMSB					Because Z0 is not used, the ZPAGEMSB
					equals PAGEMSB + 1.
PCPAGE		PC[12:6]	Z13:Z7		Program Counter page address: Page select,
					for Page Erase and Page Write
		PC[5:0]	Z6:Z1		Program Counter word address: Word select,
PCWORD					for filling temporary buffer (must be zero during
					page write operation)
Note: 1. Z15:Z14: always ignored
	Z0: should be zero for all SPM commands, byte select for the LPM instruction.
	See “Addressing the Flash during Self-Programming” on page 251 for details about the use of
	Z-pointer during Self-Programming.

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ATmega16(L)

Memory

Programming

Program And Data

Memory Lock Bits

The ATmega16 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 104. The Lock bits can only be erased to “1” with the Chip Erase command.

Table 103. Lock Bit Byte(1)

Lock Bit Byte	Bit No.	Description	Default Value
	7	–	1 (unprogrammed)
	6	–	1 (unprogrammed)
BLB12	5	Boot Lock bit	1 (unprogrammed)
BLB11	4	Boot Lock bit	1 (unprogrammed)
BLB02	3	Boot Lock bit	1 (unprogrammed)
BLB01	2	Boot Lock bit	1 (unprogrammed)
LB2	1	Lock bit	1 (unprogrammed)
LB1	0	Lock bit	1 (unprogrammed)

Note: 1. “1” means unprogrammed, “0” means programmed

Table 104. Lock Bit Protection Modes

	Memory Lock Bits(2)			Protection Type
	LB Mode	LB2	LB1
	1	1	1	No memory lock features enabled.
				Further programming of the Flash and EEPROM is
	2	1	0	disabled in Parallel and SPI/JTAG Serial Programming
				mode. The Fuse bits are locked in both Serial and Parallel
				Programming mode.(1)
				Further programming and verification of the Flash and
	3	0	0	EEPROM is disabled in Parallel and SPI/JTAG Serial
				Programming mode. The Fuse bits are locked in both
				Serial and Parallel Programming mode.(1)
	BLB0 Mode	BLB02	BLB01
	1	1	1	No restrictions for SPM or LPM accessing the Application
				section.
	2	1	0	SPM is not allowed to write to the Application section.
				SPM is not allowed to write to the Application section, and
				LPM executing from the Boot Loader section is not
	3	0	0	allowed to read from the Application section. If interrupt
				vectors are placed in the Boot Loader section, interrupts
				are disabled while executing from the Application section.
				LPM executing from the Boot Loader section is not
				allowed to read from the Application section. If interrupt
	4	0	1	vectors are placed in the Boot Loader section, interrupts
				are disabled while executing from the Application section.
	BLB1 Mode	BLB12	BLB11

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