ATmega16(L)

ATmega16

Boundary-scan

Order

Table 94 shows the scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the analog circuits, which constitute the most significant bits of the scan chain regardless of which physical pin they are connected to. In Figure 116, PXn. Data corresponds to FF0, PXn. Control corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.

Table 94. ATmega16 Boundary-scan Order

Bit Number	Signal Name	Module
140	AC_IDLE	Comparator
139	ACO
138	ACME
137	ACBG
136	COMP	ADC
135	PRIVATE_SIGNAL1(1)
134	ACLK
133	ACTEN
132	PRIVATE_SIGNAL2(2)
131	ADCBGEN
130	ADCEN
129	AMPEN
128	DAC_9
127	DAC_8
126	DAC_7
125	DAC_6
124	DAC_5
123	DAC_4
122	DAC_3
121	DAC_2
120	DAC_1
119	DAC_0
118	EXTCH
117	G10
116	G20
115	GNDEN
114	HOLD
113	IREFEN
112	MUXEN_7

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Table 94. ATmega16 Boundary-scan Order (Continued)

Bit Number	Signal Name	Module
111	MUXEN_6
110	MUXEN_5
109	MUXEN_4
108	MUXEN_3
107	MUXEN_2
106	MUXEN_1
105	MUXEN_0
104	NEGSEL_2
103	NEGSEL_1
102	NEGSEL_0
101	PASSEN
100	PRECH
99	SCTEST
98	ST
97	VCCREN
96	PB0.Data	Port B
95	PB0.Control
94	PB0.Pullup_Enable
93	PB1.Data
92	PB1.Control
91	PB1.Pullup_Enable
90	PB2.Data
89	PB2.Control
88	PB2.Pullup_Enable
87	PB3.Data
86	PB3.Control
85	PB3.Pullup_Enable
84	PB4.Data
83	PB4.Control
82	PB4.Pullup_Enable
81	PB5.Data
80	PB5.Control
79	PB5.Pullup_Enable
78	PB6.Data
77	PB6.Control
76	PB6.Pullup_Enable

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ATmega16(L)

Table 94. ATmega16 Boundary-scan Order (Continued)

	Bit Number	Signal Name	Module
	75	PB7.Data
	74	PB7.Control
	73	PB7.Pullup_Enable
	72	RSTT	Reset Logic
			(Observe-Only)
	71	RSTHV
	70	EXTCLKEN	Enable signals for main clock/Oscillators
	69	OSCON
	68	RCOSCEN
	67	OSC32EN
	66	EXTCLK (XTAL1)	Clock input and Oscillators for the main clock
			(Observe-Only)
	65	OSCCK
	64	RCCK
	63	OSC32CK
	62	TWIEN	TWI
	61	PD0.Data	Port D
	60	PD0.Control
	59	PD0.Pullup_Enable
	58	PD1.Data
	57	PD1.Control
	56	PD1.Pullup_Enable
	55	PD2.Data
	54	PD2.Control
	53	PD2.Pullup_Enable
	52	PD3.Data
	51	PD3.Control
	50	PD3.Pullup_Enable
	49	PD4.Data
	48	PD4.Control
	47	PD4.Pullup_Enable
	46	PD5.Data
	45	PD5.Control
	44	PD5.Pullup_Enable
	43	PD6.Data
	42	PD6.Control
	41	PD6.Pullup_Enable
	40	PD7.Data

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Table 94. ATmega16 Boundary-scan Order (Continued)

Bit Number	Signal Name	Module
39	PD7.Control
38	PD7.Pullup_Enable
37	PC0.Data	Port C
36	PC0.Control
35	PC0.Pullup_Enable
34	PC1.Data
33	PC1.Control
32	PC1.Pullup_Enable
31	PC6.Data
30	PC6.Control
29	PC6.Pullup_Enable
28	PC7.Data
27	PC7.Control
26	PC7.Pullup_Enable
25	TOSC	32 kHz Timer Oscillator
24	TOSCON
23	PA7.Data	Port A
22	PA7.Control
21	PA7.Pullup_Enable
20	PA6.Data
19	PA6.Control
18	PA6.Pullup_Enable
17	PA5.Data
16	PA5.Control
15	PA5.Pullup_Enable
14	PA4.Data
13	PA4.Control
12	PA4.Pullup_Enable
11	PA3.Data
10	PA3.Control
9	PA3.Pullup_Enable
8	PA2.Data
7	PA2.Control
6	PA2.Pullup_Enable
5	PA1.Data

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ATmega16(L)

Boundary-scan

Description

Language Files

Table 94. ATmega16 Boundary-scan Order (Continued)

Bit Number	Signal Name	Module
4	PA1.Control
3	PA1.Pullup_Enable
2	PA0.Data
1	PA0.Control
0	PA0.Pullup_Enable

Notes: 1. PRIVATE_SIGNAL1 should always be scanned in as zero. 2. PRIVATE:SIGNAL2 should always be scanned in as zero.

Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format used by automated test-generation software. The order and function of bits in the Boundary-scan Data Register are included in this description. A BSDL file for ATmega16 is available.

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