ATmega16(L)

Table 91. Boundary-scan Signals for the Analog Comparator

Signal	Direction as Seen from		Recommended Input	Output Values when
Name	the Comparator	Description	when Not in Use	Recommended Inputs are Used
AC_IDLE	Input	Turns off Analog	1	Depends upon µC code being
		comparator when true		executed
ACO	Output	Analog Comparator	Will become input to µC	0
		Output	code being executed
ACME	Input	Uses output signal from	0	Depends upon µC code being
		ADC mux when true		executed
ACBG	Input	Bandgap Reference	0	Depends upon µC code being
		enable		executed

Scanning the ADC

Figure 123 shows a block diagram of the ADC with all relevant control and observe signals. The Boundary-scan cell from Figure 122 is attached to each of these signals. The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well.

Figure 123. Analog to Digital Converter

VCCREN

AREF

IREFEN

	To Comparator	2.56V
		ref
MUXEN_7		PASSEN
ADC_7
MUXEN_6
ADC_6
MUXEN_5
ADC_5
MUXEN_4	SCTEST	ADCBGEN
ADC_4
EXTCH		1.22V	PRECH
MUXEN_3		ref	AREF
			AREF
ADC_3
MUXEN_2
ADC_2			DAC_9..0
MUXEN_1			10-bit DAC
ADC_1	G10	G20	ADCEN
MUXEN_0
		ACTEN
ADC_0	+
		+
NEGSEL_2	10x	20x	HOLD
ADC_2	-	-
NEGSEL_1		GNDEN
ADC_1
	ST
NEGSEL_0
	ACLK
ADC_0
	AMPEN

DACOUT

+

COMP

-

COMP

The signals are described briefly in Table 92.

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Table 92. Boundary-scan Signals for the ADC

			Recommended	Output Values when Recommended
Signal	Direction as Seen		Input when Not	Inputs are used, and CPU is not
Name	from the ADC	Description	in Use	Using the ADC
COMP	Output	Comparator Output	0	0
ACLK	Input	Clock signal to gain stages	0	0
		implemented as Switch-cap filters
ACTEN	Input	Enable path from gain stages to	0	0
		the comparator
ADCBGEN	Input	Enable Band-gap reference as	0	0
		negative input to comparator
ADCEN	Input	Power-on signal to the ADC	0	0
AMPEN	Input	Power-on signal to the gain stages	0	0
DAC_9	Input	Bit 9 of digital value to DAC	1	1
DAC_8	Input	Bit 8 of digital value to DAC	0	0
DAC_7	Input	Bit 7 of digital value to DAC	0	0
DAC_6	Input	Bit 6 of digital value to DAC	0	0
DAC_5	Input	Bit 5 of digital value to DAC	0	0
DAC_4	Input	Bit 4 of digital value to DAC	0	0
DAC_3	Input	Bit 3 of digital value to DAC	0	0
DAC_2	Input	Bit 2 of digital value to DAC	0	0
DAC_1	Input	Bit 1 of digital value to DAC	0	0
DAC_0	Input	Bit 0 of digital value to DAC	0	0
EXTCH	Input	Connect ADC channels 0 - 3 to by-	1	1
		pass path around gain stages
G10	Input	Enable 10x gain	0	0
G20	Input	Enable 20x gain	0	0
GNDEN	Input	Ground the negative input to	0	0
		comparator when true
HOLD	Input	Sample&Hold signal. Sample	1	1
		analog signal when low. Hold
		signal when high. If gain stages
		are used, this signal must go
		active when ACLK is high.
IREFEN	Input	Enables Band-gap reference as	0	0
		AREF signal to DAC
MUXEN_7	Input	Input Mux bit 7	0	0
MUXEN_6	Input	Input Mux bit 6	0	0
MUXEN_5	Input	Input Mux bit 5	0	0
MUXEN_4	Input	Input Mux bit 4	0	0
MUXEN_3	Input	Input Mux bit 3	0	0

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ATmega16(L)

Table 92. Boundary-scan Signals for the ADC (Continued)

			Recommended	Output Values when Recommended
Signal	Direction as Seen		Input when Not	Inputs are used, and CPU is not
Name	from the ADC	Description	in Use	Using the ADC
MUXEN_2	Input	Input Mux bit 2	0	0
MUXEN_1	Input	Input Mux bit 1	0	0
MUXEN_0	Input	Input Mux bit 0	1	1
NEGSEL_2	Input	Input Mux for negative input for	0	0
		differential signal, bit 2
NEGSEL_1	Input	Input Mux for negative input for	0	0
		differential signal, bit 1
NEGSEL_0	Input	Input Mux for negative input for	0	0
		differential signal, bit 0
PASSEN	Input	Enable pass-gate of gain stages.	1	1
PRECH	Input	Precharge output latch of	1	1
		comparator. (Active low)
SCTEST	Input	Switch-cap TEST enable. Output	0	0
		from x10 gain stage send out to
		Port Pin having ADC_4
ST	Input	Output of gain stages will settle	0	0
		faster if this signal is high first two
		ACLK periods after AMPEN goes
		high.
VCCREN	Input	Selects Vcc as the ACC reference	0	0
		voltage.

Note: Incorrect setting of the switches in Figure 123 will make signal contention and may damage the part. There are several input choices to the S&H circuitry on the negative input of the output comparator in Figure 123. Make sure only one path is selected from either one ADC pin, Bandgap reference source, or Ground.

If the ADC is not to be used during scan, the recommended input values from Table 92 should be used. The user is recommended not to use the Differential Gain stages during scan. Switchcap based gain stages require fast operation and accurate timing which is difficult to obtain when used in a scan chain. Details concerning operations of the differential gain stage is therefore not provided.

The AVR ADC is based on the analog circuitry shown in Figure 123 with a successive approximation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is usually to ensure that an applied analog voltage is measured within some limits. This can easily be done without running a successive approximation algorithm: apply the lower limit on the digital DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit on the digital DAC[9:0] lines, and verify the output from the comparator to be high.

The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well.

When using the ADC, remember the following:

•The Port Pin for the ADC channel in use must be configured to be an input with pull-up disabled to avoid signal contention.

•In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when enabling the ADC. The user is advised to wait at least 200 ns after enabling the ADC before

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controlling/observing any ADC signal, or perform a dummy conversion before using the first result.

•The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low (Sample mode).

As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when the power supply is 5.0V and AREF is externally connected to VCC.

The lower limit is:		1024 1,5V 0,95 ⁄ 5V				= 291 = 0x123
The upper limit is:			1024 1,5V 1,05 ⁄ 5V			= 323 = 0x143

The recommended values from Table 92 are used unless other values are given in the algorithm in Table 93. Only the DAC and Port Pin values of the Scan-chain are shown. The column “Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register with the succeeding columns. The verification should be done on the data scanned out when scanning in the data on the same row in the table.

Table 93. Algorithm for Using the ADC

									PA3.
							PA3.	PA3.	Pullup_
Step	Actions	ADCEN	DAC	MUXEN	HOLD	PRECH	Data	Control	Enable
1	SAMPLE	1	0x200	0x08	1	1	0	0	0
	_PRELO
	AD
2	EXTEST	1	0x200	0x08	0	1	0	0	0
3		1	0x200	0x08	1	1	0	0	0
4		1	0x123	0x08	1	1	0	0	0
5		1	0x123	0x08	1	0	0	0	0
6	Verify the	1	0x200	0x08	1	1	0	0	0
	COMP bit
	scanned
	out to be
	0
7		1	0x200	0x08	0	1	0	0	0
8		1	0x200	0x08	1	1	0	0	0
9		1	0x143	0x08	1	1	0	0	0
10		1	0x143	0x08	1	0	0	0	0
11	Verify the	1	0x200	0x08	1	1	0	0	0
	COMP bit
	scanned
	out to be
	1

Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock frequency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at least five times the number of scan bits divided by the maximum hold time, thold,max.

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