- •Features
- •Disclaimer
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •Resources
- •Data Retention
- •AVR CPU Core
- •Introduction
- •Status Register
- •Stack Pointer
- •I/O Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Watchdog Reset
- •Watchdog Timer
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Register Description for I/O Ports
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Timer/Counter0 and Timer/Counter1 Prescalers
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Noise Canceler
- •Force Output Compare
- •Normal Mode
- •Fast PWM Mode
- •16-bit Timer/Counter Register Description
- •8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Frame Formats
- •Parity Bit Calculation
- •Parity Generator
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Using MPCM
- •Write Access
- •Read Access
- •Features
- •TWI Terminology
- •Transferring Bits
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •SCL and SDA Pins
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •Using the TWI
- •Master Receiver Mode
- •Slave Receiver Mode
- •Miscellaneous States
- •Analog Comparator Multiplexed Input
- •Analog to Digital Converter
- •Features
- •Operation
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •Analog Input Circuitry
- •Features
- •Overview
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •IEEE 1149.1 (JTAG) Boundary-scan
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Reset Register
- •EXTEST; $0
- •IDCODE; $1
- •AVR_RESET; $C
- •BYPASS; $F
- •Scanning the ADC
- •ATmega16 Boundary-scan Order
- •Features
- •Application Section
- •Read-While-Write and no Read- While-Write Flash Sections
- •Prevent Reading the RWW Section during Self-Programming
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Programming Command Register
- •Virtual Flash Page Read Register
- •Performing Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics
- •Idle Supply Current
- •Pin Pullup
- •Pin Driver Strength
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
System Clock
and Clock
Options
Clock Systems and their Distribution
Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 32. The clock systems are detailed Figure 11.
Figure 11. Clock Distribution
Asynchronous |
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General I/O |
Timer/Counter |
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Modules |
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clkI/O
clkASY
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Timer/Counter |
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External RC |
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Oscillator |
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Oscillator |
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ADC |
CPU Core |
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RAM |
Flash and |
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EEPROM |
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clkADC |
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AVR Clock |
clkCPU |
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Control Unit |
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clkFLASH |
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Reset Logic |
Watchdog Timer |
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Source Clock |
Watchdog Clock |
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Clock |
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Watchdog |
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Multiplexer |
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Oscillator |
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External Clock |
Crystal |
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Low-frequency |
Calibrated RC |
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Oscillator |
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Crystal Oscillator |
Oscillator |
CPU Clock – clkCPU |
The CPU clock is routed to parts of the system concerned with operation of the AVR core. |
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Examples of such modules are the General Purpose Register File, the Status Register and the |
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data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing |
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general operations and calculations. |
I/O Clock – clkI/O |
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. |
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The I/O clock is also used by the External Interrupt module, but note that some external inter- |
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rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O |
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clock is halted. Also note that address recognition in the TWI module is carried out asynchro- |
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nously when clkI/O is halted, enabling TWI address reception in all sleep modes. |
Flash Clock – clkFLASH |
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- |
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taneously with the CPU clock. |
Asynchronous Timer |
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly |
Clock – clkASY |
from an external 32 kHz clock crystal. The dedicated clock domain allows using this |
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Timer/Counter as a real-time counter even when the device is in sleep mode. |
24 ATmega16(L)
2466P–AVR–08/07