JTAG Interface

and On-chip

Debug System

Features

Overview

•JTAG (IEEE std. 1149.1 Compliant) Interface

•Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard

•Debugger Access to:

–All Internal Peripheral Units

–Internal and External RAM

–The Internal Register File

–Program Counter

–EEPROM and Flash Memories

–Extensive On-chip Debug Support for Break Conditions, Including

–AVR Break Instruction

–Break on Change of Program Memory Flow

–Single Step Break

–Program Memory Breakpoints on Single Address or Address Range

–Data Memory Breakpoints on Single Address or Address Range

•Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

•On-chip Debugging Supported by AVR Studio®

The AVR IEEE std. 1149.1 compliant JTAG interface can be used for

•Testing PCBs by using the JTAG Boundary-scan capability

•Programming the non-volatile memories, Fuses and Lock bits

•On-chip Debugging

Test Access Port –

TAP

A brief description is given in the following sections. Detailed descriptions for Programming via the JTAG interface, and using the Boundary-scan Chain can be found in the sections “Programming via the JTAG Interface” on page 278 and “IEEE 1149.1 (JTAG) Boundary-scan” on page 228, respectively. The On-chip Debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third party vendors only.

Figure 112 shows a block diagram of the JTAG interface and the On-chip Debug system. The TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller selects either the JTAG Instruction Register or one of several Data Registers as the scan chain (Shift Register) between the TDI input and TDO output. The Instruction Register holds JTAG instructions controlling the behavior of a Data Register.

The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers used for board-level testing. The JTAG Programming Interface (actually consisting of several physical and virtual Data Registers) is used for JTAG Serial Programming via the JTAG interface. The Internal Scan Chain and Break Point Scan Chain are used for On-chip Debugging only.

The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the Test Access Port – TAP. These pins are:

•TMS: Test Mode Select. This pin is used for navigating through the TAP-controller state machine.

•TCK: Test Clock. JTAG operation is synchronous to TCK.

•TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains).

•TDO: Test Data Out. Serial output data from Instruction register or Data Register.

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The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided.

When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP input signals are internally pulled high and the JTAG is enabled for Boundary-scan and programming. In this case, the TAP output pin (TDO) is left floating in states where the JTAG TAP controller is not shifting data, and must therefore be connected to a pull-up resistor or other hardware having pull-ups (for instance the TDI-input of the next device in the scan chain). The device is shipped with this fuse programmed.

For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is monitored by the debugger to be able to detect external reset sources. The debugger can also pull the RESET pin low to reset the whole system, assuming only open collectors on the reset line are used in the application.

Figure 112. Block Diagram

I/O PORT 0

DEVICE BOUNDARY

					BOUNDARY SCAN CHAIN
TDI			JTAG PROGRAMMING
TDO		TAP
			INTERFACE
TCK
	CONTROLLER
TMS
					INTERNAL	AVR CPU
			FLASH	Address
					SCAN	PC
		INSTRUCTION	MEMORY	Data
					CHAIN	Instruction
		REGISTER
		ID
		REGISTER	BREAKPOINT
	M		UNIT		FLOW CONTROL
		BYPASS					ANALOG PERIPHERIAL UNITS	Analog inputs
	U				UNIT
		REGISTER				DIGITAL
	X
						PERIPHERAL
						UNITS
		BREAKPOINT
		SCAN CHAIN
						JTAG / AVR CORE
		ADDRESS				COMMUNICATION
			OCD STATUS			INTERFACE		lines
		DECODER
			AND CONTROL
								Control & Clock
					I/O PORT n

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TAP Controller

Figure 113. TAP Controller State Diagram

1 Test-Logic-Reset

		0
0			1					1
	Run-Test/Idle				Select-DR Scan
						0
				1
					Capture-DR
						0
					Shift-DR			0
						1
								1
					Exit1-DR
						0
					Pause-DR			0
						1
				0
					Exit2-DR
						1
					Update-DR
					1		0

1

Select-IR Scan

0

1	Capture-IR

		0
	Shift-IR			0
		1
				1
	Exit1-IR
		0
				0
	Pause-IR
		1
0
	Exit2-IR
		1
	Update-IR
	1		0

The TAP controller is a 16-state finite state machine that controls the operation of the Boundaryscan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions depicted in Figure 113 depend on the signal present on TMS (shown adjacent to each state transition) at the time of the rising edge at TCK. The initial state after a Power-On Reset is Test- Logic-Reset.

As a definition in this document, the LSB is shifted in and out first for all Shift Registers.

Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:

•At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift Instruction Register – Shift-IR state. While in this state, shift the four bits of the JTAG instructions into the JTAG Instruction Register from the TDI input at the rising edge of TCK. The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR state. The MSB of the instruction is shifted in when this state is left by setting TMS high. While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out

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Using the

Boundary-scan

Chain

Using the On-chip

Debug System

on the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register.

•Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The ExitIR, Pause-IR, and Exit2-IR states are only used for navigating the state machine.

•At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state. While in this state, upload the selected Data Register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be held low during input of all bits except the MSB. The MSB of the data is shifted in when this state is left by setting TMS high. While the Data Register is shifted in from the TDI pin, the parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the TDO pin.

•Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine.

As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting JTAG instruction and using Data Registers, and some JTAG instructions may select certain functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.

Note: Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be entered by holding TMS high for five TCK clock periods.

For detailed information on the JTAG specification, refer to the literature listed in “Bibliography” on page 227.

A complete description of the Boundary-scan capabilities are given in the section “IEEE 1149.1 (JTAG) Boundary-scan” on page 228.

As shown in Figure 112, the hardware support for On-chip Debugging consists mainly of:

•A scan chain on the interface between the internal AVR CPU and the internal peripheral units

•Break Point unit

•Communication interface between the CPU and JTAG system

All read or modify/write operations needed for implementing the Debugger are done by applying AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O memory mapped location which is part of the communication interface between the CPU and the JTAG system.

The Break Point Unit implements Break on Change of Program Flow, Single Step Break, 2 Program Memory Break Points, and 2 combined Break Points. Together, the 4 Break Points can be configured as either:

•4 single Program Memory Break Points

•3 Single Program Memory Break Point + 1 single Data Memory Break Point

•2 single Program Memory Break Points + 2 single Data Memory Break Points

•2 single Program Memory Break Points + 1 Program Memory Break Point with mask (“range Break Point”)

•2 single Program Memory Break Points + 1 Data Memory Break Point with mask (“range Break Point”)

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