Boot Loader

Support – Read-

While-Write

Self-

Programming

The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated protocol to read code and write (program) that code into the Flash memory, or read the code from the Program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader memory is configurable with Fuses and the Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection.

Features	•	Read-While-Write Self-Programming
	•	Flexible Boot Memory size
	•	High Security (Separate Boot Lock Bits for a Flexible Protection)
	•	Separate Fuse to Select Reset Vector
	•	Optimized Page(1) Size
	•	Code Efficient Algorithm
	•	Efficient Read-Modify-Write Support

Note: 1. A page is a section in the flash consisting of several bytes (see Table 107 on page 262) used during programming. The page organization does not affect normal operation.

Application and

Boot Loader Flash

Sections

Application Section

The Flash memory is organized in two main sections, the Application section and the Boot Loader section (see Figure 125). The size of the different sections is configured by the BOOTSZ Fuses as shown in Table 100 on page 257 and Figure 125. These two sections can have different level of protection since they have different sets of Lock bits.

The Application section is the section of the Flash that is used for storing the application code. The protection level for the application section can be selected by the Application Boot Lock bits (Boot Lock bits 0), see Table 96 on page 249. The Application section can never store any Boot Loader code since the SPM instruction is disabled when executed from the Application section.

BLS – Boot Loader While the Application section is used for storing the application code, the The Boot Loader soft- Section ware must be located in the BLS since the SPM instruction can initiate a programming when executing from the BLS only. The SPM instruction can access the entire Flash, including the BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader

Lock bits (Boot Lock bits 1), see Table 97 on page 249.

Read-While-Write and no Read- While-Write Flash Sections

Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While- Write (NRWW) section. The limit between the RWWand NRWW sections is given in Table 101 on page 257 and Figure 125 on page 248. The main difference between the two sections is:

•When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation.

•When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation.

Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax “Read-While-Write section” refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update.

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RWW – Read-While- If a Boot Loader software update is programming a page inside the RWW section, it is possible Write Section to read code from the Flash, but only code that is located in the NRWW section. During an ongoing programming, the software must ensure that the RWW section never is being read. If the user software is trying to read code that is located inside the RWW section (i.e., by a call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader section. The Boot Loader section is always located in the NRWW section. The RWW Section Busy bit (RWWSB) in the Store Program Memory Control Register (SPMCR) will be read as logical one as long as the RWW section is blocked for reading. After a programming is completed, the RWWSB must be cleared by software before reading code located in the RWW section. See “Store Program Memory Control Register – SPMCR” on page 250. for details on how to clear

RWWSB.

NRWW – No Read- The code located in the NRWW section can be read when the Boot Loader software is updating While-Write Section a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU

is halted during the entire page erase or page write operation.

Table 95. Read-While-Write Features

Which Section does the Z-	Which Section can be		Read-While-
pointer Address during the	Read during	Is the CPU	Write
Programming?	Programming?	Halted?	Supported?
RWW section	NRWW section	No	Yes
NRWW section	None	Yes	No

Figure 124. Read-While-Write vs. No Read-While-Write

Read-While-Write

(RWW) Section

	Z-pointer
	Addresses NRWW
Z-pointer	Section
Addresses RWW	No Read-While-Write
Section	(NRWW) Section
	CPU is Halted
Code Located in	during the Operation
NRWW Section
Can be Read during
the Operation

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Boot Loader Lock

Bits

Figure 125. Memory Sections(1)

No Read-While-Write Section Read-While-Write Section No Read-While-Write Section Read-While-Write Section

Program Memory

BOOTSZ = '11'

Application Flash Section

Application Flash Section

Boot Loader Flash Section

Program Memory

BOOTSZ = '01'

Application Flash Section

Application Flash Section

Boot Loader Flash Section

$0000

	Read-While-Write Section
End Application	Write-WhileSection
End RWW
Start NRWW
Flashend	-
	Read
Start Boot Loader
	No
$0000
	Read-While-Write Section
End Application	SectionWrite
End RWW
Start NRWW
Flashend	-
	-ReadWhile
Start Boot Loader
	No

Program Memory

BOOTSZ = '10'

$0000

Application Flash Section

End RWW

Start NRWW

Application Flash Section

End Application

Start Boot Loader

Boot Loader Flash Section

Flashend

Program Memory

BOOTSZ = '00'

$0000

Application flash Section

End RWW, End Application

Start NRWW, Start Boot Loader

Boot Loader Flash Section

Flashend

Note: 1. The parameters in the figure above are given in Table 100 on page 257.

If no Boot Loader capability is needed, the entire Flash is available for application code. The Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection.

The user can select:

•To protect the entire Flash from a software update by the MCU

•To protect only the Boot Loader Flash section from a software update by the MCU

•To protect only the Application Flash section from a software update by the MCU

•Allow software update in the entire Flash

See Table 96 and Table 97 for further details. The Boot Lock bits can be set in software and in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command only. The general Write Lock (Lock Bit mode 2) does not control the programming of the Flash memory by SPM instruction. Similarly, the general Read/Write Lock (Lock Bit mode 3) does not control reading nor writing by LPM/SPM, if it is attempted.

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Entering the Boot

Loader Program

Table 96. Boot Lock Bit0 Protection Modes (Application Section)(1)

	BLB0 Mode	BLB02	BLB01	Protection
	1	1	1	No restrictions for SPM or LPM accessing the Application
				section.
	2	1	0	SPM is not allowed to write to the Application section.
				SPM is not allowed to write to the Application section, and
				LPM executing from the Boot Loader section is not
	3	0	0	allowed to read from the Application section. If interrupt
				vectors are placed in the Boot Loader section, interrupts
				are disabled while executing from the Application section.
				LPM executing from the Boot Loader section is not
	4	0	1	allowed to read from the Application section. If interrupt
				vectors are placed in the Boot Loader section, interrupts
				are disabled while executing from the Application section.
	Note: 1. “1”	means	unprogrammed,	“0” means programmed

Table 97. Boot Lock Bit1 Protection Modes (Boot Loader Section)(1)

	BLB1 mode	BLB12	BLB11	Protection
	1	1	1	No restrictions for SPM or LPM accessing the Boot Loader
				section.
	2	1	0	SPM is not allowed to write to the Boot Loader section.
				SPM is not allowed to write to the Boot Loader section,
				and LPM executing from the Application section is not
	3	0	0	allowed to read from the Boot Loader section. If interrupt
				vectors are placed in the Application section, interrupts
				are disabled while executing from the Boot Loader section.
				LPM executing from the Application section is not allowed
	4	0	1	to read from the Boot Loader section. If interrupt vectors
				are placed in the Application section, interrupts are
				disabled while executing from the Boot Loader section.
	Note: 1. “1” means unprogrammed, “0” means programmed

Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset. After the application code is loaded, the program can start executing the application code. Note that the fuses cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is programmed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface.

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Store Program

Memory Control

Register – SPMCR

Table 98. Boot Reset Fuse(1)

BOOTRST	Reset Address
1	Reset Vector = Application reset (address $0000)
0	Reset Vector = Boot Loader reset (see Table 100 on page 257)

Note: 1. “1” means unprogrammed, “0” means programmed

The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.

Bit	7	6	5	4	3	2	1	0
	SPMIE	RWWSB	–	RWWSRE	BLBSET	PGWRT	PGERS	SPMEN	SPMCR
Read/Write	R/W	R	R	R/W	R/W	R/W	R/W	R/W
Initial value	0	0	0	0	0	0	0	0

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR Register is cleared.

• Bit 6 – RWWSB: Read-While-Write Section Busy

When a self-programming (Page Erase or Page Write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated.

• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in the ATmega16 and always read as zero.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

When programming (Page Erase or Page Write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while the Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lost.

• Bit 3 – BLBSET: Boot Lock Bit Set

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z- pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles.

An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 254 for details.

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Addressing the Flash during SelfProgramming

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

• Bit 0 – SPMEN: Store Program Memory Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remains high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no effect.

The Z-pointer is used to address the SPM commands.

Bit	15	14	13	12	11	10	9	8
ZH (R31)	Z15	Z14	Z13	Z12	Z11	Z10	Z9	Z8
ZL (R30)	Z7	Z6	Z5	Z4	Z3	Z2	Z1	Z0
	7	6	5	4	3	2	1	0

Since the Flash is organized in pages (see Table 107 on page 262), the Program Counter can be treated as having two different sections. One section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. This is shown in Figure 126. Note that the Page Erase and Page Write operations are addressed independently. Therefore it is of major importance that the Boot Loader software addresses the same page in both the Page Erase and Page Write operation. Once a programming operation is initiated, the address is latched and the Z-pointer can be used for other operations.

The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lock bits. The content of the Z-pointer is ignored and will have no effect on the operation. The LPM instruction does also use the Z pointer to store the address. Since this instruction addresses the Flash byte by byte, also the LSB (bit Z0) of the Z-pointer is used.

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Figure 126. Addressing the Flash during SPM(1)

BIT 15

ZPCMSB

ZPAGEMSB 1 0

Z - REGISTER

0

PROGRAM

PCMSB

PAGEMSB

PCPAGE

PCWORD

COUNTER

PAGE ADDRESS

WORD ADDRESS

WITHIN THE FLASH

WITHIN A PAGE

PROGRAM MEMORY

PAGE

PCWORD[PAGEMSB:0]:

PAGE

INSTRUCTION WORD

00

01

02

PAGEEND

Self-Programming

the Flash

Notes: 1. The different variables used in Figure 126 are listed in Table 102 on page 258. 2. PCPAGE and PCWORD are listed in Table 107 on page 262.

The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the page erase command or between a page erase and a page write operation:

Alternative 1, fill the buffer before a Page Erase

•Fill temporary page buffer

•Perform a Page Erase

•Perform a Page Write

Alternative 2, fill the buffer after Page Erase

•Perform a Page Erase

•Fill temporary page buffer

•Perform a Page Write

If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while loading since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the page erase and page write operation is addressing the same page. See “Simple Assembly Code Example for a Boot Loader” on page 256 for an assembly code example.

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