SPI Serial

Programming

Algorithm

Data Polling Flash

tion. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into $FF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz

When writing serial data to the ATmega16, data is clocked on the rising edge of SCK.

When reading data from the ATmega16, data is clocked on the falling edge of SCK. See Figure 138 for timing details.

To program and verify the ATmega16 in the SPI Serial Programming mode, the following sequence is recommended (See four byte instruction formats in Figure 116 on page 276):

1.Power-up sequence:

Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.

2.Wait for at least 20 ms and enable SPI Serial Programming by sending the Programming Enable serial instruction to pin MOSI.

3.The SPI Serial Programming instructions will not work if the communication is out of synchronization. When in sync. the second byte ($53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command.

4.The Flash is programmed one page at a time. The page size is found in Table 107 on page 262. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data Low byte must be loaded before data High byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of the address. If polling is not used,

the user must wait at least tWD_FLASH before issuing the next page. (See Table 115). Accessing the SPI Serial Programming interface before the Flash write operation completes can result in incorrect programming.

5.The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait

at least tWD_EEPROM before issuing the next byte. (See Table 115). In a chip erased device, no $FFs in the data file(s) need to be programmed.

6.Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO.

7.At the end of the programming session, RESET can be set high to commence normal operation.

8.Power-off sequence (if needed): Set RESET to “1”.

Turn VCC power off.

When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value $FF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be writ-

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WD_EEPROM

ATmega16(L)

ten. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value $FF, so when programming

this value, the user will have to wait for at least tWD_FLASH before programming the next page. As a chip erased device contains $FF in all locations, programming of addresses that are meant to

contain $FF, can be skipped. See Table 115 for tWD_FLASH value

Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $FF, but the user should have the following in mind: As a chip erased device contains $FF in all locations, programming of addresses that are meant to contain $FF, can be skipped. This does not apply if the EEPROM is re-programmed without chip erasing the device. In this case, data polling cannot be used for the value $FF, and the user will have to wait at least t before programming the next byte. See Table 115 for tWD_EEPROM value.

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Table 115. Minimum Wait Delay before Writing the Next Flash or EEPROM Location

Symbol	Minimum Wait Delay
tWD_FUSE	4.5 ms
tWD_FLASH	4.5 ms
tWD_EEPROM	9.0 ms
tWD_ERASE	9.0 ms

Serial Programming Table 116 on page 276 and Figure 137 on page 277 describes the Instruction set.

Instruction set

Table 116. Serial Programming Instruction Set (Hexadecimal values)

				Instruction Format
Instruction(1)/Operation
			Byte 1	Byte 2	Byte 3	Byte4
Programming Enable			$AC	$53	$00	$00
Chip Erase (Program Memory/EEPROM)			$AC	$80	$00	$00
			$F0	$00	$00	data byte out
Poll RDY/BSY
Load Instructions
Load Extended Address byte(1)			$4D	$00	Extended adr	$00
Load Program Memory Page, High byte			$48	adr MSB	adr LSB	high data byte in
Load Program Memory Page, Low byte			$40	adr MSB	adr LSB	low data byte in
Load EEPROM Memory Page (page access)(1)			$C1	$00	adr LSB	data byte in
Read Instructions
Read Program Memory, High byte			$28	adr MSB	adr LSB	high data byte out
Read Program Memory, Low byte			$20	adr MSB	adr LSB	low data byte out
Read EEPROM Memory			$A0	adr MSB	adr LSB	data byte out
Read Lock bits			$58	$00	$00	data byte out
Read Signature Byte			$30	$00	0000 000aa	data byte out
Read Fuse bits			$50	$00	$00	data byte out
Read Fuse High bits			$58	$08	$00	data byte out
Read Extended Fuse Bits			$50	$08	$00	data byte out
Read Calibration Byte			$38	$00	$0b00 000bb	data byte out
Write Instructions
Write Program Memory Page			$4C	000a aaaa	aa00 0000	$00
Write EEPROM Memory			$C0	adr MSB	adr LSB	data byte in
Write EEPROM Memory Page (page access)(1)			$C2	adr MSB	adr LSB	$00
Write Lock bits			$AC	$E0	$00	data byte in
Write Fuse bits			$AC	$A0	$00	data byte in
Write Fuse High bits			$AC	$A8	$00	data byte in
Write Extended Fuse Bits			$AC	$A4	$00	data byte in

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Notes: 1. Not all instructions are applicable for all parts.

2.a = address

3.Bits are programmed ‘0’, unprogrammed ‘1’.

4.To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .

5.Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size.

6.See htt://www.atmel.com/avr for Application Notes regarding programming and programmers.

If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the next instruction is carried out.

Within the same page, the low data byte must be loaded prior to the high data byte.

After data is loaded to the page buffer, program the EEPROM page, see Figure 137 on page 277.

Figure 137. Serial Programming Instruction example

Serial Programming Instruction

	Load Program Memory Page (High/Low Byte)/				Write Program Memory Page/
	Load EEPROM Memory Page (page access)				Write EEPROM Memory Page
Byte 1	Byte 2	Byte 3	Byte 4	Byte 1	Byte 2	Byte 3	Byte 4

	Adr MSB	Adr LSB		Adr MSB	Adr LSBB
Bit 15	B	0	Bit 15	B	0

Page Buffer

Page Offset

Page 0

Page 1

Page 2

Page Number

Page N-1

Program Memory/

EEPROM Memory

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SPI Serial

For characteristics of the SPI module, see “SPI Timing Characteristics” on page 295.

Programming

Characteristics

Figure 138. SPI Serial Programming Waveforms

SERIAL DATA INPUT

MSB

LSB

(MOSI)

SERIAL DATA OUTPUT

MSB

LSB

(MISO)

SERIAL CLOCK INPUT

(SCK)

Programming via

SAMPLE

Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,

the JTAG Interface

TMS, TDI and TDO. Control of the reset and clock pins is not required.

To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR must be cleared. Alternatively, if the JTD bit is set, the External Reset can be forced low. Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available for programming. This provides a means of using the JTAG pins as normal port pins in running mode while still allowing In-System Programming via the JTAG interface. Note that this technique can not be used when using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedicated for this purpose.

As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.

Programming Specific The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions JTAG Instructions useful for Programming are listed below.

The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which Data Register is selected as path between TDI and TDO for each instruction.

The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be used as an idle state between JTAG sequences. The state machine sequence for changing the instruction word is shown in Figure 139.

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