ATmega128(L)
System Control and Reset
Resetting the AVR		During reset, all I/O registers are set to their initial values, and the program starts execu-
		tion from the Reset Vector. The instruction placed at the Reset Vector must be a JMP -
		absolute jump - instruction to the reset handling routine. If the program never enables an
		interrupt source, the interrupt vectors are not used, and regular program code can be
		placed at these locations. This is also the case if the Reset Vector is in the Application
		section while the interrupt vectors are in the boot section or vice versa. The circuit dia-
		gram in Figure 21 shows the reset logic. Table 19 defines the electrical parameters of
		the reset circuitry.
		The I/O ports of the AVR are immediately reset to their initial state when a reset source
		goes active. This does not require any clock source to be running.
		After all reset sources have gone inactive, a delay counter is invoked, stretching the
		internal reset. This allows the power to reach a stable level before normal operation
		starts. The time-out period of the delay counter is defined by the user through the
		CKSEL fuses. The different selections for the delay period are presented in “Clock
		Sources” on page 34.
Reset Sources		The ATmega128 has five sources of reset:
		• Power-on Reset. The MCU is reset when the supply voltage is below the power-on
		reset threshold (VPOT).

• External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage VCC is below the brown-out reset threshold (VBOT) and the Brown-out Detector is enabled.

• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan chains of the JTAG system. Refer to the section “IEEE 1149.1 (JTAG) Boundary-scan” on page 244 for details.

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Figure 21.	Reset Logic
				DATA BUS
PEN	D	Q		MCU Control and Status
				Register (MCUCSR)
	L	Q		PORF	BORF EXTRF WDRF JTRF
	Pull-up Resistor
	Power-On Reset
	Circuit
BODEN			Brown-Out
			Reset Circuit
BODLEVEL
	Pull-up Resistor
RESET	SPIKE		Reset Circuit
	FILTER
	JTAG Reset		Watchdog		RESET
	Register		Timer		COUNTER
			Watchdog
			Oscillator
			Clock	CK	Delay Counters
			Generator		TIMEOUT
			CKSEL[3:0]
			SUT[1:0]

Table 19. Reset Characteristics(1)

Symbol		Parameter			Condition	Min	Typ	Max	Units
		Power-on Reset Threshold				TBD	TBD	2.3	V
		Voltage (rising)
VPOT
		Power-on Reset Threshold				TBD	TBD	2.3	V
		Voltage (falling)(2)
VRST				Pin Threshold Voltage		TBD	TBD	TBD	V
		RESET
tRST		Minimum pulse width on				TBD	TBD	TBD	ns
		RESET	Pin
VBOT		Brown-out Reset Threshold			BODLEVEL = 1	TBD	2.7	TBD	V
		Voltage
					BODLEVEL = 0	TBD	4.0	TBD
tBOD		Minimum low voltage period for			BODLEVEL = 1	TBD	TBD	TBD	µs
		Brown-out Detection
					BODLEVEL = 0	TBD	TBD	TBD	µs
VHYST		Brown-out Detector hysteresis				TBD	50	TBD	mV

Notes: 1. Values are guidelines only. Actual values are TBD.

2.The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)

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ATmega128(L)

Power-on Reset

A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detec-

tion level is defined in Table 19. The POR is activated whenever VCC is below the

detection level. The POR circuit can be used to trigger the start-up reset, as well as to

detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from power-on. Reach-

ing the power-on reset threshold voltage invokes the delay counter, which determines

how long the device is kept in RESET after VCC rise. The RESET signal is activated

again, without any delay, when VCC decreases below the detection level.

Figure 22. MCU Start-up,

Tied to VCC.

RESET

VCC

VPOT

VRST

RESET

TIME-OUT

tTOUT

INTERNAL

RESET

Figure 23. MCU Start-up,

Extended Externally

RESET

VCC

VPOT

VRST

RESET

TIME-OUT

tTOUT

INTERNAL

External Reset

RESET

An external reset is generated by a low level on the

pin. Reset pulses longer

RESET

than the minimum pulse width (see Table 19) will generate a reset, even if the clock is

not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST on its positive edge, the delay counter starts the MCU after the Time-out period tTOUT has expired.

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Figure 24. External Reset During Operation

CC

Brown-out Detection	ATmega128 has an on-chip brown-out detection (BOD) circuit for monitoring the VCC
	level during operation by comparing it to a fixed trigger level. The trigger level for the
	BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed),
	or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spike
	free brown-out detection. The hysteresis on the detection level should be interpreted as
	VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
	The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is
	enabled (BODEN programmed), and VCC decreases to a value below the trigger level
	(VBOT- in Figure 25), the Brown-out reset is immediately activated. When VCC increases
	above the trigger level (VBOT+ in Figure 25), the delay counter starts the MCU after the
	time-out period tTOUT has expired.
	The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level
	for longer than tBOD given in Table 19.
	Figure 25. Brown-out Reset During Operation
		VCC		VBOT-	VBOT+
		RESET
	TIME-OUT				tTOUT
	INTERNAL
		RESET
Watchdog Reset	When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle dura-
	tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period
	tTOUT. Refer to page 50 for details on operation of the Watchdog Timer.

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ATmega128(L)

Figure 26. Watchdog Reset During Operation

CC

CK

MCU Control and Status	The MCU Control and Status Register provides information on which reset source
Register – MCUCSR	caused an MCU reset.
	Bit	7		6	5	4	3	2	1	0
		JTD		-	-	JTRF	WDRF	BORF	EXTRF	PORF	MCUCSR
	Read/Write	R/W		R	R	R/W	R/W	R/W	R/W	R/W
	Initial value	0		0	0		See bit description

Internal Voltage

Reference

Note that only EXTRF and PORF are available in ATmega103 compatibility mode.

• Bit 4 - JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag.

• Bit 3 - WDRF: Watchdog Reset Flag

This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

• Bit 2 - BORF: Brown-out Reset Flag

This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

• Bit 1 - EXTRF: External Reset Flag

This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

• Bit 0 - PORF: Power-On Reset Flag

This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.

ATmega128 features an internal bandgap reference. This reference is used for Brownout Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference.

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