ATmega128(L)
		• Shift-DR: The IDCODE scan chain is shifted by the TCK input.
SAMPLE_PRELOAD; $2		Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of
		the input/output pins without affecting the system operation. However, the output
		latched are not connected to the pins. The Boundary-scan Chain is selected as Data
		Register.
		The active states are:
		• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
		• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
		• Update-DR: Data from the Boundary-scan Chain is applied to the output latches.
		However, the output latches are not connected to the pins.
AVR_RESET; $C		The AVR specific public JTAG instruction for forcing the AVR device into the Reset
		Mode or releasing the JTAG reset source. The TAP controller is not reset by this instruc-
		tion. The one bit Reset Register is selected as Data Register. Note that the reset will be
		active as long as there is a logic 'one' in the Reset Chain. The output from this chain is
		not latched.

The active states are:

•Shift-DR: The Reset Register is shifted by the TCK input.

BYPASS; $F

Mandatory JTAG instruction selecting the Bypass Register for Data Register.

The active states are:

•Capture-DR: Loads a logic “0” into the Bypass Register.

•Shift-DR: The Bypass Register cell between TDI and TDO is shifted.

Boundary-scan Related

Register in I/O Memory

MCU Control and Status	The MCU Control and Status Register contains control bits for general MCU functions,
Register – MCUCSR	and provides information on which reset source caused an MCU reset.
	Bit	7	6	5	4	3	2	1	0
		JTD	–	–	JTRF	WDRF	BORF	EXTRF	PORF	MCUCSR
	Read/Write	R/W	R	R	R/W	R/W	R/W	R/W	R/W
	Initial value	0	0	0		See bit description

• Bits 7 - JTD: JTAG Interface Disable

When this bit is zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed when changing this bit: The application software must write this bit to the desired value twice within four cycles to change its value.

• Bit 4 - JTRF: JTAG Reset Flag

Boundary-scan Chain

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag.

The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connection.

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Scanning the Digital Port Pins Figure 123 shows the Boundary-scan Cell for a bidirectional port pin with pull-up function. The cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn

– function, and a bidirectional pin cell that combines the three signals Output Control – OCxn, Output Data – ODxn, and Input Data – IDxn, into only a two-stage shift register. The port and pin indexes are not used in the following description

The Boundary-scan logic is not included in the figures in the Data Sheet. Figure 124 shows a simple digital Port Pin as described in the section “I/O-Ports” on page 60. The Boundary-scan details from Figure 123 replaces the dashed box in Figure 124.

When no alternate port function is present, the Input Data – ID corresponds to the PINxn register value (but ID has no synchronizer), Output Data corresponds to the PORT register, Output Control corresponds to the Data Direction – DD register, and the Pull-up Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn.

Digital alternate port functions are connected outside the dotted box in Figure 124 to make the scan chain read the actual pin value. For Analog function, there is a direct connection from the external pin to the analog circuit, and a scan chain is inserted on the interface between the digital logic and the analog circuitry.

Figure 123. Boundary-scan Cell for Bidirectional Port Pin with Pull-Up Function.

ShiftDR	To Next Cell		EXTEST	Vcc
Pullup Enable (PUE)			0
FF2		LD2	1
0
D	Q	D Q
1		G

Output Control (OC)

	FF1	LD1	0
	0		1
	D Q	D Q
	1	G

Output Data (OD)

	0	FF0	LD0	0
		0		Port Pin (PXn)
	1			1
		D Q	D Q
		1	G

Input Data (ID)

From Last Cell

ClockDR

UpdateDR

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ATmega128(L)

Figure 124. General Port Pin Schematic diagram

See Boundary-Scan description for details!

PUExn	PUD

			Q	D
			DDxn
			Q CLR
				WDx
OCxn			RESET
				RDx
Pxn			Q	D
ODxn			PORTxn
			Q CLR
IDxn				WPx
			RESET
SLEEP				RRx
SYNCHRONIZER				RPx
D	Q	D	Q
		PINxn
L	Q		Q
				CLK I/O

PUD:	PULLUP DISABLE	WDx:	WRITE DDRx
PUExn:	PULLUP ENABLE for pin Pxn	RDx:	READ DDRx
OCxn:	OUTPUT CONTROL for pin Pxn	WPx:	WRITE PORTx
ODxn:	OUTPUT DATA to pin Pxn	RRx:	READ PORTx REGISTER
IDxn:	INPUT DATA from pin Pxn	RPx:	READ PORTx PIN
SLEEP:	SLEEP CONTROL	CLK I/O :	I/O CLOCK

DATA BUS

Boundary-scan and the Two- The 2 Two-wire Interface pins SCL and SDA have one additional control signal in the wire Interface scan-chain; Two-wire Interface Enable – TWIEN. As shown in Figure 125, the TWIEN

signal enables a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general scan cell as shown in Figure 129 is attached to the TWIEN signal.

Notes: 1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan support for digital port pins suffice for connectivity tests. The only reason for having TWIEN in the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary-scan.

2.Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to drive contention.

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Figure 125. Additional Scan Signal for the Two-wire Interface

PUExn

Pxn

SRC

OCxn

ODxn

TWIEN

								Slew-rate limited
											IDxn
Scanning the RESET Pin	The RESET pin accepts 5V active low logic for standard reset operation, and 12V active
	high logic for High Voltage Parallel programming. An observe-only cell as shown in Fig-
	ure 126 is inserted both for the 5V reset signal; RSTT, and the 12V reset signal;
	RSTHV.
	Figure 126. Observe-only Cell
									To
								next
				ShiftDR					cell
	From system pin						FF1				To system logic
					0
				1			D	Q
	From				ClockDR
	previous
	cell
Scanning the Clock Pins	The AVR devices have many clock options selectable by fuses. These are: Internal RC
	Oscillator, External RC, External Clock, (High Frequency) Crystal Oscillator, Low Fre-
	quency Crystal Oscillator, and Ceramic Resonator.

Figure 127 shows how each oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general boundary-scan cell, while the oscillator/clock output is attached to an observe-only cell. In addition to the main clock, the timer oscillator is scanned in the same way. The output from the internal RC-Oscillator is not scanned, as this oscillator does not have external connections.

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Figure 127. Boundary-scan Cells for Oscillators and Clock Options

XTAL1/TOSC1 XTAL2/TOSC2

To

next

Oscillator

To

ShiftDR

cell

EXTEST

next

From digital logic

0

ShiftDR

cell

ENABLE

OUTPUT

To system logic

0

1

FF1

D

Q

D

Q

0

1

G

1

D

Q

From ClockDR

UpdateDR

From ClockDR

previous

cell

previous

cell

Table 102 summaries the scan registers for the external clock pin XTAL1, oscillators with XTAL1/XTAL2 connections as well as 32 kHz Timer oscillator.

Table 102. Scan Signals for the Oscillator(1)(2)(3)

	Scanned Clock		Scanned Clock Line
Enable signal	Line	Clock Option	when not Used
EXTCLKEN	EXTCLK (XTAL1)	External Clock	0
OSCON	OSCCK	External Crystal	1
		External Ceramic Resonator
RCOSCEN	RCCK	External RC	1
OSC32EN	OSC32CK	Low Freq. External Crystal	1
TOSKON	TOSCK	32 kHz Timer Oscillator	1

Notes: 1. Do not enable more than one clock source as main clock at a time.

2. Scanning an oscillator output gives unpredictable results as there is a frequency drift between the internal oscillator and the JTAG TCK clock. If possible, scanning an external clock is preferred.

	3. The clock configuration is programmed by fuses. As a fuse is not changed run-time,
	the clock configuration is considered fixed for a given application. The user is advised
	to scan the same clock option as to be used in the final system. The enable signals
	are supported in the scan chain because the system logic can disable clock options
	in sleep modes, thereby disconnecting the oscillator pins from the scan path if not
	provided. The INTCAP fuses are not supported in the scan-chain, so the boundary
	scan chain can not make a XTAL oscillator requiring internal capacitors to run unless
	the fuse is correctly programmed.
Scanning the Analog	The relevant Comparator signals regarding Boundary-scan are shown in Figure 128.
Comparator	The Boundary-scan cell from Figure 129 is attached to each of these signals. The sig-
	nals are described in Table 103.
	The Comparator need not be used for pure connectivity testing, since all analog inputs
	are shared with a digital port pin as well.

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Figure 128. Analog comparator

BANDGAP

REFERENCE

ACBG

ACO

AC_IDLE

ACME

ADCEN

ADC MULTIPLEXER

OUTPUT

Figure 129. General Boundary-scan Cell used for Signals for Comparator and ADC

To

next

ShiftDR

cell

EXTEST

From digital logic/

0

From analog ciruitry

To analog circuitry/

0

1

To digital logic

D

Q

D Q

1

G

From ClockDR UpdateDR

previous

cell

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