- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •ATmega103 Compatibility
- •Address Latch Requirements
- •Pull-up and Bus-keeper
- •Timing
- •XMEM Register Description
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •System Control and Reset
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watch Dog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Alternate Functions of Port F
- •Alternate Functions of Port G
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Port C Data Register – PORTC
- •Port D Data Register – PORTD
- •Port E Data Register – PORTE
- •Port F Data Register – PORTF
- •Port G Data Register – PORTG
- •External Interrupts
- •8-bit Timer/Counter0 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •16-bit Timer/Counter Register Description
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter2 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Overview
- •Description
- •Timing Example
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Dual USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Multi-master Bus Systems, Arbitration and Synchronization
- •Overview of the TWI Module
- •Scl and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Analog to Digital Converter
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0:
- •ADLAR = 1:
- •Features
- •Overview
- •Test Access Port – TAP
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Device Identification Register
- •Reset Register
- •Boundary-scan Chain
- •EXTEST; $0
- •IDCODE; $1
- •SAMPLE_PRELOAD; $2
- •AVR_RESET; $C
- •BYPASS; $F
- •Boundary-scan Chain
- •Scanning the Digital Port Pins
- •Scanning the RESET Pin
- •Scanning the Clock Pins
- •Scanning the ADC
- •Boot Loader Features
- •Application Section
- •Boot Loader Section – BLS
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •PROG_COMMANDS ($5)
- •PROG_PAGELOAD ($6)
- •PROG_PAGEREAD ($7)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Virtual Flash Page Read Register
- •Programming Algorithm
- •Entering Programming Mode
- •Leaving Programming Mode
- •Performing Chip Erase
- •Programming the Flash
- •Reading the Flash
- •Programming the EEPROM
- •Reading the EEPROM
- •Programming the Fuses
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •2-wire Serial Interface Characteristics
- •ADC Characteristics - Preliminary Data
- •External Data Memory Timing
- •Ordering Information
- •Packaging Information
Table 124. Command Byte Bit Coding
Command Byte |
Command Executed |
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0000 1000 |
Read Signature Bytes and Calibration byte |
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0000 0100 |
Read Fuse and Lock Bits |
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0000 0010 |
Read Flash |
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0000 0011 |
Read EEPROM |
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Table 125. No. of Words in a Page and no. of Pages in the Flash
Flash Size |
Page Size |
PCWORD |
No. of Pages |
PCPAGE |
PCMSB |
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64K words (128K bytes) |
128 words |
PC[6:0] |
512 |
PC[15:7] |
15 |
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Table 126. No. of Words in a Page and no. of Pages in the EEPROM
EEPROM Size |
Page Size |
PCWORD |
No. of Pages |
PCPAGE |
EEAMSB |
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4K bytes |
8 bytes |
EEA[2:0] |
512 |
EEA[11:3] |
8 |
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Parallel Programming
Enter Programming Mode |
The following algorithm puts the device in parallel programming mode: |
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Apply 4.5 - 5.5 V between VCC and GND. |
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2. |
Set |
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to “0” and toggle XTAL1 at least 6 times |
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RESET |
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Set the Prog_enable pins listed in Table 122 on page 283 to “0000” and wait at |
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least 100 ns. |
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4. |
Apply 11.5 - 12.5V to |
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Any activity on Prog_enable pins within 100 ns |
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RESET. |
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after +12V has been applied to |
RESET, |
will cause the device to fail entering pro- |
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gramming mode. |
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Considerations for Efficient |
The loaded command and address are retained in the device during programming. For |
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Programming |
efficient programming, the following should be considered. |
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The command needs only be loaded once when writing or reading multiple memory |
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locations. |
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Skip writing the data value $FF, that is the contents of the entire EEPROM (unless |
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the EESAVE fuse is programmed) and Flash after a Chip Erase. |
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Address high byte needs only be loaded before programming or reading a new 256 |
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word window in Flash or 256-byte EEPROM. This consideration also applies to |
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Signature bytes reading. |
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Chip Erase |
The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock |
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bits are not reset until the program memory has been completely erased. The Fuse bits |
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are not changed. A Chip Erase must be performed before the Flash is reprogrammed. |
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Note: 1. The EEPRPOM memory is preserved during chip erase if the EESAVE fuse is |
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programmed. |
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Load Command “Chip Erase” |
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Set XA1, XA0 to “10”. This enables command loading. |
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2. |
Set BS1 to “0”. |
284 ATmega128(L)
2467B–09/01
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ATmega128(L) |
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3. |
Set DATA to “1000 0000”. This is the command for Chip Erase. |
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4. |
Give XTAL1 a positive pulse. This loads the command. |
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5. |
Give |
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goes low. |
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WR |
a negative pulse. This starts the Chip Erase. RDY/BSY |
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6. |
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goes high before loading a new command. |
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Wait until RDY/BSY |
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Programming the Flash |
The Flash is organized in pages, see Table 124 on page 283. When programming the |
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Flash, the program data is latched into a page buffer. This allows one page of program |
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data to be programmed simultaneously. The following procedure describes how to pro- |
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gram the entire Flash memory: |
A. Load Command “Write Flash”
1.Set XA1, XA0 to '10'. This enables command loading.
2.Set BS1 to '0'.
3.Set DATA to '0001 0000'. This is the command for Write Flash.
4.Give XTAL1 a positive pulse. This loads the command.
B. Load Address Low byte
1.Set XA1, XA0 to '00'. This enables address loading.
2.Set BS1 to '0'. This selects low address.
3.Set DATA = Address low byte ($00 - $FF).
4.Give XTAL1 a positive pulse. This loads the address low byte.
C. Load Data Low Byte
1.Set XA1, XA0 to '01'. This enables data loading.
2.Set DATA = Data low byte ($00 - $FF).
3.Give XTAL1 a positive pulse. This loads the data byte.
D. Load Data High Byte
1.Set BS1 to '1'. This selects high data byte.
2.Set XA1, XA0 to '01'. This enables data loading.
3.Set DATA = Data high byte ($00 - $FF).
4.Give XTAL1 a positive pulse. This loads the data byte.
E. Latch Data
1.Set BS1 to '1'. This selects high data byte.
2.Give PAGEL a positive pulse. This latches the data bytes. (See Figure 137 for signal waveforms)
F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.
While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in Figure 136 on page 286. Note
that if less than 8 bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write.
G. Load Address High byte
1.Set XA1, XA0 to '00'. This enables address loading.
2.Set BS1 to '1'. This selects high address.
3.Set DATA = Address high byte ($00 - $FF).
4.Give XTAL1 a positive pulse. This loads the address high byte.
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H. Program Page
1.Set BS1 = “0”
2.Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSYgoes low.
3.Wait until RDY/BSY goes high. (See Figure 137 for signal waveforms)
I.Repeat B through H until the entire Flash is programmed or until all data has been programmed.
J.End Page Programming
1.1. Set XA1, XA0 to '10'. This enables command loading.
2.Set DATA to '0000 0000'. This is the command for No Operation.
3.Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset.
Figure 136. Addressing the Flash which is Organized in Pages
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PROGRAM |
PCMSB |
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PAGEMSB |
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PCPAGE |
PCWORD |
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COUNTER |
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PAGE ADDRESS |
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WORD ADDRESS |
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WITHIN THE FLASH |
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WITHIN A PAGE |
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PROGRAM MEMORY |
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PAGE |
PCWORD[PAGEMSB:0]: |
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PAGE |
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INSTRUCTION WORD |
00 |
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PAGEEND
Note: 1. PCPAGE and PCWORD are listed in Table 125 on page 284.
286 ATmega128(L)
2467B–09/01
ATmega128(L)
Figure 137. Programming the Flash Waveforms
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F |
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A |
B |
C |
D |
E |
B |
C |
D |
E |
G |
H |
DATA |
$10 |
ADDR. LOW |
DATA LOW |
DATA HIGH |
XX |
ADDR. LOW |
DATA LOW |
DATA HIGH |
XX |
ADDR. HIGH |
XX |
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XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Note: “XX” is don’t care. The letters refer to the programming description above.
Programming the EEPROM The EEPROM is organized in pages, see Table 125 on page 284. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of
data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” on page 285 for details on
Command, Address and Data loading):
1.A: Load Command “0001 0001”.
2.G: Load Address High Byte ($00 - $FF)
3.B: Load Address Low Byte ($00 - $FF)
4.C: Load Data ($00 - $FF)
5.E: Latch data (give PAGEL a positive pulse)
K:Repeat 3 through 5 until the entire buffer is filled
L:Program EEPROM page
1.Set BS1 to “0”.
2.Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low.
3.Wait until to RDY/BSY goes high before programming the next page. (See Figure 138 for signal waveforms)
287
2467B–09/01