Alternate Functions of Port C In ATmega103 compatibility mode, Port C is output only. The Port C has an alternate function as the address high byte for the External Memory Interface.

Table 33. Port C Pins Alternate Functions

Port Pin	Alternate Function
PC7	A15
PC6	A14
PC5	A13
PC4	A12
PC3	A11
PC2	A10
PC1	A9
PC0	A8

Table 34 and Table 35 relate the alternate functions of Port C to the overriding signals shown in Figure 32 on page 66.

Table 34. Overriding Signals for Alternate Functions in PC7..PC4

Signal
Name	PC7/A15	PC6/A14	PC5/A13	PC4/A12
PUOE	SRE • (XMM(1)<1)	SRE • (XMM<2)	SRE • (XMM<3)	SRE • (XMM<4)
PUOV	0	0	0	0
DDOE	SRE • (XMM<1)	SRE • (XMM<2)	SRE • (XMM<3)	SRE • (XMM<4)
DDOV	1	1	1	1
PVOE	SRE • (XMM<1)	SRE • (XMM<2)	SRE • (XMM<3)	SRE • (XMM<4)
PVOV	A11	A10	A9	A8
DIEOE	0	0	0	0
DIEOV	0	0	0	0
DI	–	–	–	–
AIO	–	–	–	–

Note: 1. XMM = 0 in ATmega103 compatibility mode.

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Table 35. Overriding Signals for Alternate Functions in PC3..PC0(1)

Signal
Name	PC3/A11	PC2/A10	PC1/A9	PC0/A8
PUOE	SRE • (XMM<5)	SRE • (XMM<6)	SRE • (XMM<7)	SRE • (XMM<7)
PUOV	0	0	0	0
DDOE	SRE • (XMM<5)	SRE • (XMM<6)	SRE • (XMM<7)	SRE • (XMM<7)
DDOV	1	1	1	1
PVOE	SRE • (XMM<5)	SRE • (XMM<6)	SRE • (XMM<7)	SRE • (XMM<7)
PVOV	A11	A10	A9	A8
DIEOE	0	0	0	0
DIEOV	0	0	0	0
DI	–	–	–	–
AIO	–	–	–	–

Note: 1. XMM = 0 in ATmega103 compatibility mode.

Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 36.

Table 36. Port D Pins Alternate Functions

Port Pin	Alternate Function
PD7	T2 (Timer/Counter2 Clock Input)
PD6	T1 (Timer/Counter1 Clock Input)
PD5	XCK1(1) (USART1 external clock input/output)
PD4	IC1 (Timer/Counter1 Input Capture Trigger)
PD3	INT3/TXD1(1) (External Interrupt3 Input or UART1 Transmit Pin)
PD2	INT2/RXD1(1) (External Interrupt2 Input or UART1 Receive Pin)
PD1	INT1/SDA(1) (External Interrupt1 Input or TWI Serial DAta)
PD0	INT0/SCL(1) (External Interrupt0 Input or TWI Serial CLock)

Note: 1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibility mode.

The alternate pin configuration is as follows:

• T2 - Port D, Bit 7

T2, Timer/Counter2 counter source.

• T1 - Port D, Bit 6

T1, Timer/Counter1 counter source.

• XCK1 - Port D, Bit 4

XCK1, USART1 external clock. The Data Direction Register (DDD4) controls whether the clock is output (DDD4 set) or input (DDD4 cleared). The XCK1 pin is active only when the USART1 operates in synchronous mode.

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• IC1 - Port D, Bit 4

IC1 - Input Capture Pin1: The PD4 pin can act as an input capture pin for

Timer/Counter1.

• INT3/TXD1 - Port D, Bit 3

INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the MCU.

TXD1, Transmit Data (Data output pin for the USART1). When the USART1 transmitter is enabled, this pin is configured as an output regardless of the value of DDD3.

• INT2/RXD1 - Port D, Bit 2

INT2, External Interrupt source 2. The PD2 pin can serve as an external interrupt source to the MCU.

RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit.

• INT1/SDA - Port D, Bit 1

INT1, External Interrupt source 1. The PD1 pin can serve as an external interrupt source to the MCU.

SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation.

• INT0/SCL - Port D, Bit 0

INT0, External Interrupt source 0. The PD0 pin can serve as an external interrupt source to the MCU.

SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation.

Table 37 and Table 38 relates the alternate functions of Port D to the overriding signals shown in Figure 32 on page 66.

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Table 37. Overriding Signals for Alternate Functions PD7..PD4

Signal Name	PD7/T2	PD6/T1	PD5/XCK1	PD4/IC1
PUOE	0	0	0	0
PUOV	0	0	0	0
DDOE	0	0	0	0
DDOV	0	0	0	0
PVOE	0	0	UMSEL1	0
PVOV	0	0	XCK1 OUTPUT	0
DIEOE	0	0	0	0
DIEOV	0	0	0	0
DI	T2 INPUT	T1 INPUT	XCK1 INPUT	IC1 INPUT
AIO	–	–	–	–

Table 38. Overriding Signals for Alternate Functions in PD3..PD0(1)

Signal Name	PD3/INT3/TXD1	PD2/INT2/RXD1			PD1/INT1/SDA			PD0/INT0/SCL
PUOE	TXEN1	RXEN1			TWEN			TWEN
PUOV	0	PORTD2 •			PORTD1 •			PORTD0 •
			PUD			PUD			PUD
DDOE	TXEN1	RXEN1			TWEN			TWEN
DDOV	1	0			SDA_OUT			SCL_OUT
PVOE	TXEN1	0			TWEN			TWEN
PVOV	TXD1	0			0			0
DIEOE	INT3 ENABLE	INT2 ENABLE			INT1 ENABLE			INT0 ENABLE
DIEOV	1	1			1			1
DI	INT3 INPUT	INT2 INPUT/RXD1			INT1 INPUT			INT0 INPUT
AIO	–	–			SDA INPUT			SCL INPUT

Note: 1. When enabled, the Two-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module.

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