ATmega128(L)

The following code examples show how to do an atomic write of the TCNTn register contents. Writing any of the OCRnA/B/C or ICRn registers can be done by using the same principle.

Assembly Code Example

TIM16_WriteTCNTn:

; Save global interrupt flag in r18,SREG

; Disable interrupts

cli

; Set TCNTn to r17:r16 out TCNTnH,r17

out TCNTnL,r16

; Restore global interrupt flag out SREG,r18

ret

C Code Example

void TIM16_WriteTCNTn( unsigned int i )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */ sreg = SREG;

/* Disable interrupts */ _CLI();

/* Set TCNTn to i */ TCNTn = i;

/* Restore global interrupt flag */ SREG = sreg;

}

Note: The example code assumes that the part specific header file is included.

For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNTn.

Reusing the Temporary High If writing to more than one 16-bit register where the high byte is the same for all registers Byte Register written, then the high byte only needs to be written once. However, note that the same

rule of atomic operation described previously also applies in this case.

Timer/Counter Clock The Timer/Counter can be clocked by an internal or an external clock source. The clock

Sources source is selected by the clock select logic which is controlled by the clock select (CSn2:0) bits located in the Timer/Counter control register B (TCCRnB). For details on clock sources and prescaler, see “Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers” on page 138.

Counter Unit

The main part of the 16-bit Timer/Counter is the programmable 16-bit bidirectional counter unit. Figure 46 shows a block diagram of the counter and its surroundings.

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	Figure 46. Counter Unit Block Diagram
	DATABUS (8-bit)
			TOVn
			(Int.Req.)
	TEMP (8-bit)
				Clock Select
		Count		Edge	Tn
	TCNTnH (8-bit) TCNTnL (8-bit)	Clear	clkTn	Detector
		Control Logic
	TCNTn (16-bit Counter)	Direction
				( From Prescaler )
		TOP	BOTTOM

Signal description (internal signals):

Count Increment or decrement TCNTn by 1.

Direction Select between increment and decrement.

Clear Clear TCNTn (set all bits to zero).

clkTn

Timer/counter clock.

TOP Signalize that TCNTn has reached maximum value.

BOTTOM Signalize that TCNTn has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high (TCNTnH) containing the upper 8 bits of the counter, and counter low (TCNTnL) containing the lower 8 bits. The TCNTnH register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNTnH value when the TCNTnL is read, and TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNTn register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance.

Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkTn). The clkTn can be generated from an external or internal clock source, selected by the clock select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of whether clkTn is present or not. A CPU write overrides (has priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the waveform generation mode bits (WGMn3:0) located in the Timer/Counter control registers A and B (TCCRnA and TCCRnB). There are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs OCnx. For more details

about advanced counting sequences and waveform generation, see “Modes of Operation” on page 117.

The Timer/Counter overflow (TOVn) flag is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.

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