- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •ATmega103 Compatibility
- •Address Latch Requirements
- •Pull-up and Bus-keeper
- •Timing
- •XMEM Register Description
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •System Control and Reset
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watch Dog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Alternate Functions of Port F
- •Alternate Functions of Port G
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Port C Data Register – PORTC
- •Port D Data Register – PORTD
- •Port E Data Register – PORTE
- •Port F Data Register – PORTF
- •Port G Data Register – PORTG
- •External Interrupts
- •8-bit Timer/Counter0 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •16-bit Timer/Counter Register Description
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter2 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Overview
- •Description
- •Timing Example
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Dual USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Multi-master Bus Systems, Arbitration and Synchronization
- •Overview of the TWI Module
- •Scl and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Analog to Digital Converter
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0:
- •ADLAR = 1:
- •Features
- •Overview
- •Test Access Port – TAP
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Device Identification Register
- •Reset Register
- •Boundary-scan Chain
- •EXTEST; $0
- •IDCODE; $1
- •SAMPLE_PRELOAD; $2
- •AVR_RESET; $C
- •BYPASS; $F
- •Boundary-scan Chain
- •Scanning the Digital Port Pins
- •Scanning the RESET Pin
- •Scanning the Clock Pins
- •Scanning the ADC
- •Boot Loader Features
- •Application Section
- •Boot Loader Section – BLS
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •PROG_COMMANDS ($5)
- •PROG_PAGELOAD ($6)
- •PROG_PAGEREAD ($7)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Virtual Flash Page Read Register
- •Programming Algorithm
- •Entering Programming Mode
- •Leaving Programming Mode
- •Performing Chip Erase
- •Programming the Flash
- •Reading the Flash
- •Programming the EEPROM
- •Reading the EEPROM
- •Programming the Fuses
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •2-wire Serial Interface Characteristics
- •ADC Characteristics - Preliminary Data
- •External Data Memory Timing
- •Ordering Information
- •Packaging Information
ATmega128(L)
8-bit Timer/Counter0 with PWM and Asynchronous Operation
Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are:
•Single Channel Counter
•Clear Timer on Compare Match (Auto Reload)
•Glitch-free, Phase Correct Pulse Width Modulator (PWM)
•Frequency Generator
•10-bit Clock Prescaler
•Overflow and Compare Match Interrupt Sources (TOV0 and OCF0)
•Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock
Overview |
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 33. For the |
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actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible |
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I/O registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O |
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register and bit locations are listed in the “8-bit Timer/Counter Register Description” on |
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page 98. |
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Figure 33. 8-bit Timer/Counter Block Diagram |
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TCCRn |
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count |
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TOVn |
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clear |
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Control Logic |
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(Int.Req.) |
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clkTn |
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direction |
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TOSC1 |
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BOTTOM |
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TOP |
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T/C |
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Prescaler |
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Oscillator |
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Timer/Counter |
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TCNTn |
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= 0 |
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= 0xFF |
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clk I/O |
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OCn |
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(Int.Req.) |
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Waveform |
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OCn |
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Generation |
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DATABUS |
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OCRn |
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Synchronized Status flags |
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clk I/O |
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Status flags |
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Synchronization Unit |
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clk ASY |
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ASSRn |
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asynchronous mode |
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select (ASn) |
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Registers |
The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers. |
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Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag |
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Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask reg- |
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ister (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are |
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shared by other timer units. |
87
2467B–09/01
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The Timer/Counter can be clocked internally, via the prescaler, or asynchronously |
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clocked from the TOSC1/2 pins, as detailed later in this chapter. The asynchronous |
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operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select |
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logic block controls which clock source the Timer/Counter uses to increment (or decre- |
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ment) its value. The Timer/Counter is inactive when no clock source is selected. The |
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output from the clock select logic is referred to as the timer clock (clkT0). |
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The double buffered Output Compare Register (OCR0) is compared with the |
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Timer/Counter value at all times. The result of the compare can be used by the wave- |
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form generator to generate a PWM or variable frequency output on the Output Compare |
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Pin (OC0). See “Output Compare Unit” on page 89. for details. The compare match |
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event will also set the compare flag (OCF0) which can be used to generate an output |
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compare interrupt request. |
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Definitions |
Many register and bit references in this document are written in general form. A lower |
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case “n” replaces the Timer/Counter number, in this case 0. However, when using the |
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register or bit defines in a program, the precise form must be used (i.e., TCNT0 for |
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accessing Timer/Counter0 counter value and so on). |
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The definitions in Table 51 are also used extensively throughout the document. |
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Table 51. Definitions |
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BOTTOM |
The counter reaches the BOTTOM when it becomes zero (0x00) |
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MAX |
The counter reaches its MAXimum when it becomes 0xFF (decimal 255). |
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TOP |
The counter reaches the TOP when it becomes equal to the highest |
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value in the count sequence. The TOP value can be assigned to be the |
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fixed value 0xFF (MAX) or the value stored in the OCR0 register. The |
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assignment is dependent on the mode of operation. |
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Timer/Counter Clock
Sources
Counter Unit
The Timer/Counter can be clocked by an internal synchronous or an external asynchro-
nous clock source. The clock source clkT0 is by default equal to the MCU clock, clkI/O. When the AS0 bit in the ASSR register is written to logic one, the clock source is taken
from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “Asynchronous Status Register – ASSR” on page 101. For details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 104.
The main part of the 8-bit Timer/Counter is the programmable bidirectional counter unit. Figure 34 shows a block diagram of the counter and its surrounding environment.
Figure 34. Counter Unit Block Diagram
DATA BUS
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TOVn |
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(Int.Req.) |
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count |
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clk Tn |
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T/C |
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TOSC1 |
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clear |
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TCNTn |
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Control Logic |
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Prescaler |
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Oscillator |
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direction |
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TOSC2 |
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bottom |
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top |
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clkI/O |
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88 ATmega128(L)
2467B–09/01