On-chip Debug Specific

JTAG Instructions

PRIVATE0; $8

•2 single Program Memory break-points + 1 Data Memory break point with mask “range break point”.

A debugger, like the AVR Studio®, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user.

A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on page 242.

The JTAGEN fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN fuse must be programmed and no lock bits must be set for the On-chip debug system to work. As a security feature, the On-chip Debug system is disabled when any lock bits are set. Otherwise, the On-chip Debug system would have provided a back-door into a secured device.

The AVR Studio enables the user to fully control execution of programs on an AVR device with On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator. AVR Studio supports source level execution of Assembly programs assembled with Atmel Corporation’s AVR Assembler and C programs compiled with 3rd party vendors’ compilers.

AVR Studio runs under Microsoft® Windows® 95/98/2000 and Windows NT®.

For a full description of the AVR Studio, please refer to the AVR Studio User Guide. Only highlights are presented in this document.

All necessary execution commands are available in AVR Studio, both on source level and on disassembly level. The user can execute the program, single step through the code either by tracing into or stepping over functions, step out of functions, place the cursor on a statement and execute until the statement is reached, stop the execution, and reset the execution target. In addition, the user can have an unlimited number of code breakpoints (using the BREAK instruction) and up to 2 data memory breakpoints, alternatively combined as a mask (range) break-point.

The On-chip debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third-party vendors only. Instruction opcodes are listed for reference.

Private JTAG instruction for accessing On-chip debug system.

PRIVATE1; $9	Private JTAG instruction for accessing On-chip debug system.
PRIVATE2; $A	Private JTAG instruction for accessing On-chip debug system.
PRIVATE3; $B	Private JTAG instruction for accessing On-chip debug system.

On-chip Debug Related

Register in I/O Memory

On-chip Debug Register –

OCDR

Bit	7	6	5	4	3	2	1	0
	MSB/IDRD							LSB	OCDR
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial value	0	0	0	0	0	0	0	0

The OCDR register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing

242 ATmega128(L)

2467B–09/01

Using the JTAG

Programming

Capabilities

Bibliography

2467B–09/01

ATmega128(L)

to this location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate to the debugger that the register has been written. When the CPU reads the OCDR register the 7 LSB will be from the OCDR register, while the MSB is the IDRD bit. The debugger clears the IDRD bit when it has read the information.

In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR register can only be accessed if the OCDEN fuse is programmed, and the debugger enables access to the OCDR register. In all other cases, the standard I/O location is accessed.

Refer to the debugger documentation for further information on how to use this register.

Programming of AVR parts via JTAG is performed via the four-pin JTAG port, TCK, TMS, TDI and TDO. These are the only pins that need to be controlled/observed to perform JTAG programming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN fuse must be programmed and the JTD bit in the MCUSR register must be cleared to enable the JTAG Test Access Port.

The JTAG programming capability supports:

•Flash programming and verifying

•EEPROM programming and verifying

•Fuse programming and verifying

•Lock bit programming and verifying

The lock bit security is exactly as in parallel programming mode. If the lock-bits LB1 or LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a security feature that ensures no back-door exists for reading out the content of a secured device.

The details on programming through the JTAG interface and programming specific JTAG instructions are given in the section “Programming Via the JTAG Interface” on page 297.

For more information about general Boundary-scan, the following literature can be consulted:

•IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993

•Colin Maunder: The Board Designers Guide to Testable Logic Circuits, AddisonWesley, 1992

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