- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •ATmega103 Compatibility
- •Address Latch Requirements
- •Pull-up and Bus-keeper
- •Timing
- •XMEM Register Description
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •System Control and Reset
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watch Dog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Alternate Functions of Port F
- •Alternate Functions of Port G
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Port C Data Register – PORTC
- •Port D Data Register – PORTD
- •Port E Data Register – PORTE
- •Port F Data Register – PORTF
- •Port G Data Register – PORTG
- •External Interrupts
- •8-bit Timer/Counter0 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •16-bit Timer/Counter Register Description
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter2 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Overview
- •Description
- •Timing Example
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Dual USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Multi-master Bus Systems, Arbitration and Synchronization
- •Overview of the TWI Module
- •Scl and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Analog to Digital Converter
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0:
- •ADLAR = 1:
- •Features
- •Overview
- •Test Access Port – TAP
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Device Identification Register
- •Reset Register
- •Boundary-scan Chain
- •EXTEST; $0
- •IDCODE; $1
- •SAMPLE_PRELOAD; $2
- •AVR_RESET; $C
- •BYPASS; $F
- •Boundary-scan Chain
- •Scanning the Digital Port Pins
- •Scanning the RESET Pin
- •Scanning the Clock Pins
- •Scanning the ADC
- •Boot Loader Features
- •Application Section
- •Boot Loader Section – BLS
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •PROG_COMMANDS ($5)
- •PROG_PAGELOAD ($6)
- •PROG_PAGEREAD ($7)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Virtual Flash Page Read Register
- •Programming Algorithm
- •Entering Programming Mode
- •Leaving Programming Mode
- •Performing Chip Erase
- •Programming the Flash
- •Reading the Flash
- •Programming the EEPROM
- •Reading the EEPROM
- •Programming the Fuses
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •2-wire Serial Interface Characteristics
- •ADC Characteristics - Preliminary Data
- •External Data Memory Timing
- •Ordering Information
- •Packaging Information
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interrupt-driven data transmission is used, the data register empty Interrupt routine must |
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either write new data to UDR in order to clear UDRE or disable the data register empty |
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interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. |
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The Transmit Complete (TXC) flag bit is set one when the entire frame in the transmit |
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shift register has been shifted out and there are no new data currently present in the |
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transmit buffer. The TXC flag bit is automatically cleared when a transmit complete inter- |
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rupt is executed, or it can be cleared by writing a one to its bit location. The TXC flag is |
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useful in half-duplex communication interfaces (like the RS485 standard), where a |
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transmitting application must enter receive mode and free the communication bus |
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immediately after completing the transmission. |
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When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART |
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Transmit Complete Interrupt will be executed when the TXC flag becomes set (provided |
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that global interrupts are enabled). When the transmit complete interrupt is used, the |
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interrupt handling routine does not have to clear the TXC flag, this is done automatically |
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when the interrupt is executed. |
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Parity Generator |
The parity generator calculates the parity bit for the serial frame data. When parity bit is |
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enabled (UPM1 = 1), the transmitter control logic inserts the parity bit between the last |
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data bit and the first stop bit of the frame that is sent. |
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Disabling the Transmitter |
The disabling of the transmitter (setting the TXEN to zero) will not become effective until |
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ongoing and pending transmissions are completed, i.e. when the transmit shift register |
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and transmit buffer register do not contain data to be transmitted. When disabled, the |
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transmitter will no longer override the TxD pin. |
Data Reception – The
USART Receiver
The USART receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB register to one. When the receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer clock.
Receiving Frames with 5 to 8 Data Bits
The receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCK clock, and shifted into the receive shift register until the first stop bit of a frame is received. A second stop bit will be ignored by the receiver. When the first stop bit is received, i.e. a complete serial frame is present in the receive shift register, the contents of the shift register will be moved into the receive buffer. The receive buffer can then be read by reading the UDR I/O location.
174 ATmega128(L)
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ATmega128(L)
The following code example shows a simple USART receive function based on polling of the Receive Complete (RXC) flag. When using frames with less than eight bits the most significant bits of the data read from the UDR will be masked to zero. The USART has to be initialized before the function can be used.
Assembly Code Example(1)
USART_Receive:
; Wait for data to be received sbis UCSRA, RXC
rjmp USART_Receive
; Get and return received data from buffer in r16, UDR
ret
C Code Example(1)
unsigned char USART_Receive( void )
{
/* Wait for data to be received */ while ( !(UCSRA & (1<<RXC)) )
;
/* Get and return received data from buffer */ return UDR;
}
Note: 1. The example code assumes that the part specific header file is included.
For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The function simply waits for data to be present in the receive buffer by checking the
RXC flag, before reading the buffer and returning the value.
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2467B–09/01
Receiving Frames with 9 Data Bits
If 9 bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and UPE status flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR and UPE bits, which all are stored in the FIFO, will change.
The following code example shows a simple USART receive function that handles both nine bit characters and the status bits.
Assembly Code Example(1)
USART_Receive:
; Wait for data to be received
sbis UCSRA, RXC rjmp USART_Receive
; Get status and 9th bit, then data from buffer
in |
r18, UCSRA |
in |
r17, UCSRB |
in |
r16, UDR |
; If error, return -1 |
|
andi |
r18,(1<<FE)|(1<<DOR)|(1<<UPE) |
breq |
USART_ReceiveNoError |
ldi |
r17, HIGH(-1) |
ldi |
r16, LOW(-1) |
USART_ReceiveNoError:
; Filter the 9th bit, then return lsr r17
andi r17, 0x01 ret
C Code Example(1)
unsigned int USART_Receive( void )
{
unsigned char status, resh, resl; /* Wait for data to be received */ while ( !(UCSRA & (1<<RXC)) )
;
/* Get status and 9th bit, then data */ /* from buffer */
status = UCSRA; resh = UCSRB; resl = UDR;
/* If error, return -1 */
if ( status & (1<<FE)|(1<<DOR)|(1<<UPE) ) return -1;
/* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << 8) | resl);
}
Note: 1. The example code assumes that the part specific header file is included.
For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
176 ATmega128(L)
2467B–09/01
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ATmega128(L) |
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The receive function example reads all the I/O registers into the register file before any |
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computation is done. This gives an optimal receive buffer utilization since the buffer |
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location read will be free to accept new data as early as possible. |
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Receive Compete Flag and |
The USART receiver has one flag that indicates the receiver state. |
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Interrupt |
The Receive Complete (RXC) flag indicates if there are unread data present in the |
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receive buffer. This flag is one when unread data exist in the receive buffer, and zero |
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when the receive buffer is empty (i.e. does not contain any unread data). If the receiver |
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is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit |
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will become zero. |
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When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART |
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Receive Complete Interrupt will be executed as long as the RXC flag is set (provided |
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that global interrupts are enabled). When interrupt-driven data reception is used, the |
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receive complete routine must read the received data from UDR in order to clear the |
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RXC flag, otherwise a new interrupt will occur once the interrupt routine terminates. |
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Receiver Error Flags |
The USART receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and |
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Parity Error (UPE). All can be accessed by reading UCSRA. Common for the error flags |
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is that they are located in the receive buffer together with the frame for which they indi- |
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cate the error status. Due to the buffering of the error flags, the UCSRA must be read |
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before the receive buffer (UDR), since reading the UDR I/O location changes the buffer |
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read location. Another equality for the error flags is that they can not be altered by soft- |
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ware doing a write to the flag location. However, all flags must be set to zero when the |
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UCSRA is written for upward compatibility of future USART implementations. None of |
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the error flags can generate interrupts. |
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The Frame Error (FE) flag indicates the state of the first stop bit of the next readable |
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frame stored in the receive buffer. The FE flag is zero when the stop bit was correctly |
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read (as one), and the FE flag will be one when the stop bit was incorrect (zero). This |
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flag can be used for detecting out-of-sync conditions, detecting break conditions and |
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protocol handling. The FE flag is not affected by the setting of the USBS bit in UCSRC |
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since the receiver ignores all, except for the first, stop bits. For compatibility with future |
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devices, always set this bit to zero when writing to UCSRA. |
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The Data OverRun (DOR) flag indicates data loss due to a receiver buffer full condition. |
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A data overrun occurs when the receive buffer is full (two characters), it is a new charac- |
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ter waiting in the receive shift register, and a new start bit is detected. If the DOR flag is |
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set there was one or more serial frame lost between the frame last read from UDR, and |
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the next frame read from UDR. For compatibility with future devices, always write this bit |
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to zero when writing to UCSRA. The DOR flag is cleared when the frame received was |
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successfully moved from the shift register to the receive buffer. |
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The Parity Error (UPE) flag indicates that the next frame in the receive buffer had a par- |
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ity error when received. If parity check is not enabled the UPE bit will always be read |
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zero. For compatibility with future devices, always set this bit to zero when writing to |
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UCSRA. For more details see “Parity Bit Calculation” on page 170 and “Parity Checker” |
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on page 177. |
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Parity Checker |
The parity checker is active when the high USART Parity Mode (UPM1) bit is set. Type |
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of parity check to be performed (odd or even) is selected by the UPM0 bit. When |
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enabled, the parity checker calculates the parity of the data bits in incoming frames and |
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compares the result with the parity bit from the serial frame. The result of the check is |
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stored in the receive buffer together with the received data and stop bits. The Parity |
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Error (UPE) flag can then be read by software to check if the frame had a parity error. |
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177 |
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2467B–09/01 |
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