Electrical Characteristics

Absolute Maximum Ratings*

..................................Operating Temperature					-55°C to +125°C	*NOTICE: Stresses beyond those listed under “Absolute
						Maximum Ratings” may cause permanent dam-
Storage Temperature .....................................					-65°C to +150°C	age to the device. This is a stress rating only and
						functional operation of the device at these or
Voltage on any Pin except			RESET			other conditions beyond those indicated in the
with respect to Ground ................................					- 1.0V to VCC+0.5V	operational sections of this specification is not
Voltage on		with respect to Ground			-1.0V to +13.0V	implied. Exposure to absolute maximum rating
	RESET					conditions for extended periods may affect
Maximum Operating Voltage					6.0V	device reliability.
DC Current per I/O Pin ...............................................					40.0 mA
DC Current VCC and GND Pins................................					200.0 mA

DC Characteristics

TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted)

Symbol

Parameter

Condition

Min

Typ

Max

Units

VIL

Input Low Voltage

Except XTAL1 pin

TBD

TBD(1)

V

VIL1

Input Low Voltage

XTAL1 pin, External

TBD

TBD(1)

V

Clock Selected

V

IH

Input High Voltage

Except XTAL1 and

TBD(2)

TBD

V

RESET pins

V

IH1

Input High Voltage

XTAL1 pin, External

TBD(2)

TBD

V

Clock Selected

V

Input High Voltage

pin

TBD(2)

TBD

V

IH2

RESET

VOL

Output Low Voltage(3)

IOL = 20 mA, VCC = 5V

TBD

V

(Ports A,B,C,D)

IOL = 10 mA, VCC = 3V

TBD

V

VOH

Output High Voltage(4)

I

OH

= -20 mA, V

CC

= 5V

TBD

V

(Ports A,B,C,D)

IOH = -10 mA, VCC = 3V

TBD

V

IIL

Input Leakage

Vcc = 5.5V, pin low

TBD

µA

Current I/O Pin

(absolute value)

IIH

Input Leakage

Vcc = 5.5V, pin high

TBD

nA

Current I/O Pin

(absolute value)

RRST

Reset Pull-up Resistor

TBD

TBD

kΩ

Rpu

I/O Pin Pull-up Resistor

TBD

TBD

kΩ

310 ATmega128(L)

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ATmega128(L)

TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted)				(Continued)
Symbol	Parameter	Condition		Min		Typ	Max	Units
		Active 4 MHz, VCC = 3V					TBD	mA
		(ATmega128L)
		Active 8 MHz, VCC = 5V					TBD	mA
		(ATmega128)
	Power Supply Current
ICC		Idle 4 MHz, VCC = 3V					TBD	mA
		(ATmega128L)
		Idle 8 MHz, VCC = 5V					TBD	mA
		(ATmega128)
	Power-down mode(5)	WDT enabled, VCC = 3V				TBD	TBD	µA
		WDT disabled, VCC = 3V				TBD	TBD	µA
VACIO	Analog Comparator	VCC = 5V					TBD	mV
	Input Offset Voltage	Vin = VCC/2
IACLK	Analog Comparator	VCC = 5V		TBD			TBD	nA
	Input Leakage Current	Vin = VCC/2
tACID	Analog Comparator	VCC = 2.7V				TBD		ns
	Initialization Delay	VCC = 4.0V				TBD
tACID	Analog Comparator	VCC = 2.7V				TBD		ns
	Propagation Delay	VCC = 4.0V				TBD
Notes: 1.	“Max” means the highest value where the pin is guaranteed to be read as low

2.“Min” means the lowest value where the pin is guaranteed to be read as high

3.Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed:

TQFP Package:

1] The sum of all IOL, for all ports, should not exceed 400 mA.

2] The sum of all IOL, for ports A0-A7, should not exceed 100 mA. 3] The sum of all IOL, for ports B0-B3, should not exceed 100 mA. 4] The sum of all IOL, for ports B4-B7, should not exceed 100 mA. 5] The sum of all IOL, for ports C0-C3, should not exceed 100 mA. 6] The sum of all IOL, for ports C4-C7, should not exceed 100 mA.

7] The sum of all IOL, for ports D0-D3 and XTAL2, should not exceed 100 mA. 8] The sum of all IOL, for ports D4-D7, should not exceed 100 mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.

4.Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed:

TQFP Package:

1] The sum of all IOH, for all ports, should not exceed 400 mA.

2] The sum of all IOH, for ports A0-A7, should not exceed 100 mA. 3] The sum of all IOH, for ports B0-B3, should not exceed 100 mA. 4] The sum of all IOH, for ports B4-B7, should not exceed 100 mA. 5] The sum of all IOH, for ports C0-C3, should not exceed 100 mA. 6] The sum of all IOH, for ports C4-C7, should not exceed 100 mA.

7] The sum of all IOH, for ports D0-D3 and XTAL2, should not exceed 100 mA. 8] The sum of all IOH, for ports D4-D7, should not exceed 100 mA

If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.

5.Minimum VCC for Power-down is 2.5V.

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External Clock Drive

Waveforms

External Clock Drive

Figure 152. External Clock Drive Waveforms

VIH1

VIL1

Table 133. External Clock Drive

			VCC = 2.7V to 5.5V			VCC = 4.5V to 5.5V
Symbol	Parameter		Min		Max	Min		Max	Units
1/tCLCL	Oscillator Frequency		0		TBD	0		TBD	MHz
tCLCL	Clock Period		TBD			TBD			ns
tCHCX	High Time		TBD			TBD			ns
tCLCX	Low Time		TBD			TBD			ns
tCLCH	Rise Time				1.6			0.5	µs
tCHCL	Fall Time				1.6			0.5	µs
Table 134. External RC Oscillator, Typical Frequencies
	R [kΩ]			C [pF]				f
	100			70				TBD
	31.5			20				TBD
	6.5			20				TBD

Note: R should be in the range 3 kΩ - 100 kΩ, and C should be at least 20 pF. The C values given in the table includes pin capacitance. This will vary with package type.

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ATmega128(L)

2-wire Serial Interface Characteristics

Table 135 describes the requirements for devices connected to the 2-wire Serial Bus. The ATmega128 2-wire Serial Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 153.

Table 135. 2-wire Serial Bus Requirements

Symbol

Parameter

Condition

Min

Max

Units

VIL

Input Low-voltage

-0.5

0.3 VCC

V

VIH

Input High-voltage

0.7 VCC

VCC + 0.5

V

(1)

Hysteresis of Schmitt Trigger Inputs

(2)

-

V

Vhys

0.05 VCC

V

(1)

Output Low-voltage

3 mA sink current

0

0.4

V

OL

tr(1)

Rise Time for both SDA and SCL

20 + 0.1Cb(3)(2)

300

ns

t

(1)

Output Fall Time from V

IHmin

to V

ILmax

10 pF < C < 400 pF(3)

20 + 0.1C

(3)(2)

250

ns

of

b

b

tSP(1)

Spikes Suppressed by Input Filter

0

50(2)

ns

Ii

Input Current each I/O Pin

0.1VCC < Vi < 0.9VCC

-10

10

µA

C (1)

Capacitance for each I/O Pin

-

10

pF

i

f

SCL

SCL Clock Frequency

f

(4) > max(16f

, 250kHz)(5)

0

400

kHz

CK

SCL

fSCL ≤ 100 kHz

VCC – 0,4V

1000ns

Ω

----------------------------

-------------------

Rp

Value of Pull-up resistor

3mA

Cb

fSCL > 100 kHz

VCC – 0,4V

300ns

Ω

----------------------------

---------------

3mA

Cb

tHD;STA

Hold Time (repeated) START Condition

fSCL ≤ 100 kHz

4.0

-

µs

fSCL > 100 kHz

0.6

-

µs

tLOW

Low Period of the SCL Clock

fSCL ≤ 100 kHz(6)

4.7

-

µs

fSCL > 100 kHz(7)

1.3

-

µs

tHIGH

High period of the SCL clock

fSCL ≤ 100 kHz

4.0

-

µs

fSCL > 100 kHz

0.6

-

µs

tSU;STA

Set-up time for a repeated START condition

fSCL ≤ 100 kHz

4.7

-

µs

fSCL > 100 kHz

0.6

-

µs

tHD;DAT

Data hold time

fSCL ≤ 100 kHz

0

3.45

µs

fSCL > 100 kHz

0

0.9

µs

tSU;DAT

Data setup time

fSCL ≤ 100 kHz

250

-

ns

fSCL > 100 kHz

100

-

ns

tSU;STO

Setup time for STOP condition

fSCL ≤ 100 kHz

4.0

-

µs

fSCL > 100 kHz

0.6

-

µs

tBUF

Bus free time between a STOP and START

fSCL ≤ 100 kHz

4.7

-

µs

condition

Notes: 1. In ATmega128, this parameter is characterized and not 100% tested.

2.Required only for fSCL > 100 kHz.

3.Cb = capacitance of one bus line in pF.

4.fCK = CPU clock frequency

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SPI Timing

Characteristics

5.This requirement applies to all ATmega128 2-wire Serial Interface operation. Other

devices connected to the 2-wire Serial Bus need only obey the general fSCL requirement.

6.The actual low period generated by the ATmega128 2-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.

7.The actual low period generated by the ATmega128 2-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega128 devices connected to the bus may communicate at full speed (400 kHz) with other ATmega128 devices, as well as any other device with a proper tLOW acceptance margin.

Figure 153. 2-wire Serial Bus Timing

tof

tHIGH

tr

SCL

tSU;STA

tLOW

tLOW

tHD;STA

tHD;DAT

t

SDA

SU;DAT

tSU;STO

tBUF

See Figure 154 and Figure 155 for details.

Table 136. SPI Timing Parameters

Description

Mode

Min

Typ

Max

1

SCK period

Master

See Table 72

2

SCK high/low

Master

50% duty cycle

3

Rise/Fall time

Master

TBD

4

Setup

Master

TBD

5

Hold

Master

TBD

6

Out to SCK

Master

TBD

7

SCK to out

Master

TBD

8

SCK to out high

Master

TBD

ns

9

SS low to out

Slave

TBD

10

SCK period

Slave

4 • tck

TBD

11

SCK high/low

Slave

2 • tck

TBD

12

Rise/Fall time

Slave

TBD

13

Setup

Slave

TBD

14

Hold

Slave

TBD

15

SCK to out

Slave

TBD

16

SCK to

high

Slave

TBD

SS

17

high to tri-state

Slave

TBD

SS

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ATmega128(L)

Figure 154. SPI Interface Timing Requirements (Master Mode)

	SS
	6			1
	SCK
	(CPOL = 0)
			2	2
	SCK
	(CPOL = 1)
	4	5		3
	MISO	MSB	...	LSB
	(Data Input)
			7	8
	MOSI	MSB	...	LSB
	(Data Output)

Figure 155. SPI Interface Timing Requirements (Slave Mode)

SS

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

(Data Input)

MISO

(Data Output)

9

13

		10	16
	11	11
14			12
MSB	...	LSB
	15		17
MSB	...	LSB	X

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