- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •ATmega103 Compatibility
- •Address Latch Requirements
- •Pull-up and Bus-keeper
- •Timing
- •XMEM Register Description
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •System Control and Reset
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watch Dog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Alternate Functions of Port F
- •Alternate Functions of Port G
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Port C Data Register – PORTC
- •Port D Data Register – PORTD
- •Port E Data Register – PORTE
- •Port F Data Register – PORTF
- •Port G Data Register – PORTG
- •External Interrupts
- •8-bit Timer/Counter0 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •16-bit Timer/Counter Register Description
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter2 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Overview
- •Description
- •Timing Example
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Dual USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Multi-master Bus Systems, Arbitration and Synchronization
- •Overview of the TWI Module
- •Scl and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Analog to Digital Converter
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0:
- •ADLAR = 1:
- •Features
- •Overview
- •Test Access Port – TAP
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Device Identification Register
- •Reset Register
- •Boundary-scan Chain
- •EXTEST; $0
- •IDCODE; $1
- •SAMPLE_PRELOAD; $2
- •AVR_RESET; $C
- •BYPASS; $F
- •Boundary-scan Chain
- •Scanning the Digital Port Pins
- •Scanning the RESET Pin
- •Scanning the Clock Pins
- •Scanning the ADC
- •Boot Loader Features
- •Application Section
- •Boot Loader Section – BLS
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •PROG_COMMANDS ($5)
- •PROG_PAGELOAD ($6)
- •PROG_PAGEREAD ($7)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Virtual Flash Page Read Register
- •Programming Algorithm
- •Entering Programming Mode
- •Leaving Programming Mode
- •Performing Chip Erase
- •Programming the Flash
- •Reading the Flash
- •Programming the EEPROM
- •Reading the EEPROM
- •Programming the Fuses
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •2-wire Serial Interface Characteristics
- •ADC Characteristics - Preliminary Data
- •External Data Memory Timing
- •Ordering Information
- •Packaging Information
Slave Receiver Mode |
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In the slave receiver mode, a number of data bytes are received from a master transmit- |
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ter (see Figure 99). All the status codes mentioned in this chapter assume that the |
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prescaler bits are zero or are masked to zero. |
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Figure 99. Data Transfer in Slave Receiver Mode |
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VCC |
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Device 1 |
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Device 2 |
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Device 3 |
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Device n |
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R1 |
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R2 |
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SLAVE |
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MASTER |
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RECEIVER |
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TRANSMITTER |
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SDA |
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SCL |
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To initiate the slave receiver mode, TWAR and TWCR must be initialized as follows:
TWAR |
TWA6 |
TWA5 |
TWA4 |
TWA3 |
TWA2 |
TWA1 |
TWA0 |
TWGCE |
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value |
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Device’s own slave address |
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The upper 7 bits are the address to which the 2-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore the general call address.
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
X |
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TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgment of the device’s own slave address or the general call address. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been received, the TWINT flag is set and a valid status code can be read from TWSR. The status code is used to
determine the appropriate software action. The appropriate action to be taken for each status code is detailed in Table 89. The slave receiver mode may also be entered if arbi-
tration is lost while the TWI is in the master mode (see states $68 and $78).
If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA after the next received data byte. This can be used to indicate that the slave is not able to receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave address. However, the 2-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the 2-wire Serial Bus.
In all sleep modes other than Idle Mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock low during the wake up and until the TWINT flag is cleared (by writing it to one). Further data reception will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is
210 ATmega128(L)
2467B–09/01
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ATmega128(L) |
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set up with a long start-up time, the SCL line may be held low for a long time, blocking |
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other data transmissions. |
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Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte |
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present on the bus when waking up from these Sleep Modes. |
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Table 89. Status Codes for Slave Receiver Mode |
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Status Code |
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Application Software Response |
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(TWSR) |
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To TWCR |
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Prescaler Bits |
Status of the 2-wire Serial Bus and |
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To/from TWDR |
STA |
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STO |
TWINT |
TWEA |
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are 0 |
2-wire Serial Interface Hardware |
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Next Action Taken by TWI Hardware |
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$60 |
Own SLA+W has been received; |
No TWDR action or |
X |
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0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
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ACK has been returned |
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returned |
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No TWDR action |
X |
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0 |
1 |
1 |
Data byte will be received and ACK will be returned |
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$68 |
Arbitration lost in SLA+R/W as |
No TWDR action or |
X |
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0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
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master; own SLA+W has been |
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returned |
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received; ACK has been returned |
No TWDR action |
X |
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0 |
1 |
1 |
Data byte will be received and ACK will be returned |
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$70 |
General call address has been |
No TWDR action or |
X |
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0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
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received; ACK has been returned |
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returned |
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No TWDR action |
X |
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0 |
1 |
1 |
Data byte will be received and ACK will be returned |
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$78 |
Arbitration lost in SLA+R/W as |
No TWDR action or |
X |
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0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
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master; General call address has |
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returned |
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been received; ACK has been |
No TWDR action |
X |
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0 |
1 |
1 |
Data byte will be received and ACK will be returned |
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returned |
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$80 |
Previously addressed with own |
Read data byte or |
X |
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0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
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SLA+W; data has been received; |
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returned |
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ACK has been returned |
Read data byte |
X |
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0 |
1 |
1 |
Data byte will be received and ACK will be returned |
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$88 |
Previously addressed with own |
Read data byte or |
0 |
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1 |
0 |
Switched to the not addressed slave mode; |
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SLA+W; data has been received; |
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no recognition of own SLA or GCA |
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NOT ACK has been returned |
Read data byte or |
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1 |
1 |
Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1” |
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Read data byte or |
1 |
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0 |
1 |
0 |
Switched to the not addressed slave mode; |
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no recognition of own SLA or GCA; |
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a START condition will be transmitted when the bus |
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becomes free |
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Read data byte |
1 |
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0 |
1 |
1 |
Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1”; |
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a START condition will be transmitted when the bus |
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becomes free |
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$90 |
Previously addressed with |
Read data byte or |
X |
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0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
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general call; data has been re- |
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returned |
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ceived; ACK has been returned |
Read data byte |
X |
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0 |
1 |
1 |
Data byte will be received and ACK will be returned |
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$98 |
Previously addressed with |
Read data byte or |
0 |
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1 |
0 |
Switched to the not addressed slave mode; |
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general call; data has been |
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no recognition of own SLA or GCA |
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received; NOT ACK has been |
Read data byte or |
0 |
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0 |
1 |
1 |
Switched to the not addressed slave mode; |
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returned |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1” |
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Read data byte or |
1 |
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0 |
1 |
0 |
Switched to the not addressed slave mode; |
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no recognition of own SLA or GCA; |
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a START condition will be transmitted when the bus |
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becomes free |
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Read data byte |
1 |
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0 |
1 |
1 |
Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1”; |
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a START condition will be transmitted when the bus |
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becomes free |
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$A0 |
A STOP condition or repeated |
Read data byte or |
0 |
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0 |
1 |
0 |
Switched to the not addressed slave mode; |
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START condition has been |
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no recognition of own SLA or GCA |
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received while still addressed as |
Read data byte or |
0 |
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0 |
1 |
1 |
Switched to the not addressed slave mode; |
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slave |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1” |
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Read data byte or |
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0 |
1 |
0 |
Switched to the not addressed slave mode; |
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no recognition of own SLA or GCA; |
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a START condition will be transmitted when the bus |
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becomes free |
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Read data byte |
1 |
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1 |
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Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1”; |
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a START condition will be transmitted when the bus |
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becomes free |
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211 |
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2467B–09/01 |
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Figure 100. Formats and States in the Slave Receiver Mode
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Reception of the |
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S |
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SLA |
W |
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DATA |
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DATA |
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P or S |
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own slave address |
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and one or more |
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data bytes. All are |
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acknowledged |
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$60 |
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$80 |
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$80 |
$A0 |
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Last data byte received |
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P or S |
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is not acknowledged |
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$88 |
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Arbitration lost as master |
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and addressed as slave |
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$68 |
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Reception of the general call |
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General Call |
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DATA |
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address and one or more data |
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bytes |
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$70 |
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$90 |
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$90 |
$A0 |
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Last data byte received is |
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P or S |
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not acknowledged |
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$98 |
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Arbitration lost as master and |
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addressed as slave by general call |
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$78 |
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Any number of data bytes |
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From master to slave |
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DATA |
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A |
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and their associated acknowledge bits |
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From slave to master |
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n |
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This number (contained in TWSR) corresponds |
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to a defined state of the 2-Wire Serial Bus. The |
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prescaler bits are zero or masked to zero |
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Slave Transmitter Mode |
In the slave transmitter mode, a number of data bytes are transmitted to a master |
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receiver (see Figure 101). All the status codes mentioned in this chapter assume that |
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the prescaler bits are zero or are masked to zero. |
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Figure 101. Data Transfer in Slave Transmitter Mode |
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VCC |
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Device 1 |
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Device 2 |
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Device 3 |
........ |
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Device n |
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R1 |
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R2 |
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SLAVE |
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MASTER |
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TRANSMITTER |
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RECEIVER |
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SDA
SCL
To initiate the slave transmitter mode, TWAR and TWCR must be initialized as follows:
212 ATmega128(L)
2467B–09/01
ATmega128(L)
TWAR |
TWA6 |
TWA5 |
TWA4 |
TWA3 |
TWA2 |
TWA1 |
TWA0 |
TWGCE |
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value |
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Device’s own slave address |
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The upper 7 bits are the address to which the 2-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore the general call address.
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
X |
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TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgment of the device’s own slave address or the general call address. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After its own slave address and the write bit have been received, the TWINT flag is set and a valid status code can be read from TWSR. The status code is used to
determine the appropriate software action. The appropriate action to be taken for each status code is detailed in Table 90. The slave transmitter mode may also be entered if
arbitration is lost while the TWI is in the master mode (see state $B0).
If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the transfer. State $C0 or state $C8 will be entered, depending on whether the master receiver transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed slave mode, and will ignore the master if it continues the transfer. Thus the master receiver receives all “1” as serial data. State $C8 is entered if the master demands additional data bytes (by transmitting ACK), even though the slave has transmitted the last byte (TWEA zero and expecting NACK from the master).
While TWEA is zero, the TWI does not respond to its own slave address. However, the 2-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the 2-wire Serial Bus.
In all sleep modes other than Idle Mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low during the wake up and until the TWINT flag is cleared (by writing it to one). Further data transmission will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these Sleep Modes.
213
2467B–09/01
Table 90. Status Codes for Slave Transmitter Mode
Status Code |
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Application Software Response |
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(TWSR) |
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To TWCR |
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Prescaler Bits |
Status of the 2-wire Serial Bus and |
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To/from TWDR |
STA |
STO |
TWINT |
TWEA |
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are 0 |
2-wire Serial Interface Hardware |
Next Action Taken by TWI Hardware |
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$A8 |
Own SLA+R has been received; |
Load data byte or |
X |
0 |
1 |
0 |
Last data byte will be transmitted and NOT ACK should |
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ACK has been returned |
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be received |
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Load data byte |
X |
0 |
1 |
1 |
Data byte will be transmitted and ACK should be re- |
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ceived |
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$B0 |
Arbitration lost in SLA+R/W as |
Load data byte or |
X |
0 |
1 |
0 |
Last data byte will be transmitted and NOT ACK should |
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master; own SLA+R has been |
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be received |
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received; ACK has been returned |
Load data byte |
X |
0 |
1 |
1 |
Data byte will be transmitted and ACK should be re- |
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ceived |
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$B8 |
Data byte in TWDR has been |
Load data byte or |
X |
0 |
1 |
0 |
Last data byte will be transmitted and NOT ACK should |
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transmitted; ACK has been |
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be received |
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received |
Load data byte |
X |
0 |
1 |
1 |
Data byte will be transmitted and ACK should be re- |
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ceived |
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$C0 |
Data byte in TWDR has been |
No TWDR action or |
0 |
0 |
1 |
0 |
Switched to the not addressed slave mode; |
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transmitted; NOT ACK has been |
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no recognition of own SLA or GCA |
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received |
No TWDR action or |
0 |
0 |
1 |
1 |
Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1” |
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No TWDR action or |
1 |
0 |
1 |
0 |
Switched to the not addressed slave mode; |
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no recognition of own SLA or GCA; |
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a START condition will be transmitted when the bus |
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becomes free |
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No TWDR action |
1 |
0 |
1 |
1 |
Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1”; |
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a START condition will be transmitted when the bus |
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becomes free |
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$C8 |
Last data byte in TWDR has been |
No TWDR action or |
0 |
0 |
1 |
0 |
Switched to the not addressed slave mode; |
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transmitted (TWEA = “0”); ACK |
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no recognition of own SLA or GCA |
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has been received |
No TWDR action or |
0 |
0 |
1 |
1 |
Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1” |
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No TWDR action or |
1 |
0 |
1 |
0 |
Switched to the not addressed slave mode; |
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no recognition of own SLA or GCA; |
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a START condition will be transmitted when the bus |
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becomes free |
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No TWDR action |
1 |
0 |
1 |
1 |
Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1”; |
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a START condition will be transmitted when the bus |
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becomes free |
Figure 102. Formats and States in the Slave Transmitter Mode
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Reception of the |
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S |
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SLA |
R |
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A |
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DATA |
A |
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DATA |
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P or S |
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own slave address |
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A |
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and one or |
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more data bytes |
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$A8 |
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$B8 |
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$C0 |
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Arbitration lost as master |
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A |
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$B0 |
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Last data byte transmitted. |
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A |
All 1's |
P or S |
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Switched to not addressed |
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slave (TWEA = '0') |
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$C8 |
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Any number of data bytes |
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From master to slave |
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DATA |
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and their associated acknowledge bits |
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From slave to master |
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n |
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This number (contained in TWSR) corresponds |
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to a defined state of the 2-Wire Serial Bus. The |
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prescaler bits are zero or masked to zero
214 ATmega128(L)
2467B–09/01