Watchdog Timer

Watchdog Timer Control

Register – WDTCR

The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted from 16 to 2048 ms. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny26(L) resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to page 36.

To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer Control Register for details.

Figure 43. Watchdog Timer

Normally 1 MHz			WATCHDOG
			PRESCLALER

WATCHDOG

RESET

WDP0

WDP1

WDP2

WDE

						MCU RESET
Bit	7	6	5	4	3	2	1	0
$21 ($41)	–	–	–	WDCE	WDE	WDP2	WDP1	WDP0	WDTCR
Read/Write	R	R	R	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the ATtiny26(L) and will always read as zero.

• Bit 4 – WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In Safety Level 1 and 2, this bit must also be set when changing the prescaler bits.

• Bit 3 – WDE: Watchdog Enable

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can be cleared only when the WDCE bit is set(one). To disable an enabled Watchdog Timer, the following procedure must be followed:

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1.In the same operation, write a logical one to WDCE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts.

2.Within the next four clock cycles, write a logical 0 to WDE. This disables the Watchdog.

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in Table 38.

Table 38. Watchdog Timer Prescale Select(1)

			Number of WDT		Typical Time-out	Typical Time-out
WDP2	WDP1	WDP0	Oscillator Cycles		at VCC = 3.0V	at VCC = 5.0V
0	0	0	16K	(16,384)	17.1 ms	16.3 ms
0	0	1	32K	(32,768)	34.3 ms	32.5 ms
0	1	0	64K	(65,536)	68.5 ms	65 ms
0	1	1	128K	(131,072)	0.14 s	0.13 s
1	0	0	256K	(262,144)	0.27 s	0.26 s
1	0	1	512K	(524,288)	0.55 s	0.52 s
1	1	0	1,024K	(1,048,576)	1.1 s	1.0 s
1	1	1	2,048K	(2,097,152)	2.2 s	2.1 s

Note: 1. The frequency of the Watchdog Oscillator is voltage dependent. The WDR – Watchdog Reset – instruction should always be executed before the Watchdog Timer is enabled. This ensures that the reset period will be in accordance with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the Watchdog Timer may not start counting from zero.

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Universal Serial

Interface – USI

Overview

The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load. The main features of the USI are:

•Two-wire Synchronous Data Transfer (Master or Slave, fSCLmax = fCK/16)

•Three-wire Synchronous Data Transfer (Master, fSCKmax = fCK/2, Slave fSCKmax = fCK/4)

•Data Received Interrupt

•Wakeup from Idle Mode

•In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode

•Two-wire Start Condition Detector with Interrupt Capability

A simplified block diagram of the USI is shown on Figure 44.

Figure 44. Universal Serial Interface, Block Diagram
										PB1	DO
								D Q			(Output only)
								LE
										PB0	DI/SDA
											(Input/Open Drain)
	Bit7							Bit0
								3
					USIDR			2
								1	TIM0 OVF
								0
								3	0		SCK/SCL
								2		PB2
									1		(Input/Open Drain)
	USISIF	USIOIF	USIPF	USIDC		4-bit Counter
BUS								1
								0		CLOCK
										HOLD
DATA									[1]	Two-wire Clock
					USISR
										Control Unit
						2
	USISIE	USIOIE	USIWM1	USIWM0	USICS1	USICS0	USICLK	USITC
					USICR

The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and outgoing data. The register has no buffering so the data must be read as quickly as possible to ensure that no data is lost. The most significant bit is connected to one of two output pins depending of the wire mode configuration. A transparent latch is inserted between the serial register output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration.

The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the serial register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the number of bits. The clock can be selected from three different sources: the SCK pin, Timer 0 overflow, or from software.

The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows.

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