- •Features
- •Pin Configuration
- •Description
- •Block Diagram
- •Pin Descriptions
- •AVCC
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •XTAL1
- •XTAL2
- •Resources
- •AVR CPU Core
- •Architectural Overview
- •I/O Direct
- •Data Direct
- •Data Indirect with Displacement
- •Data Indirect
- •Memories
- •SRAM Data Memory
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected Pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Register Description for I/O Ports
- •Interrupts
- •Interrupt Vectors
- •Interrupt Handling
- •Interrupt Response Time
- •External Interrupt
- •Pin Change Interrupt
- •Timer/Counters
- •Timer/Counter0 Prescaler
- •Timer/Counter1 Prescaler
- •8-bit Timer/Counter0
- •8-bit Timer/Counter1
- •Timer/Counter1 in PWM Mode
- •Watchdog Timer
- •Overview
- •Register Descriptions
- •Functional Descriptions
- •Three-wire Mode
- •SPI Slave Operation Example
- •Two-wire Mode
- •Start Condition Detector
- •Alternative USI Usage
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •Changing Channel or Reference Selection
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •ADC Characteristics
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATtiny26 Rev. B/C/D
- •Table of Contents
ATtiny26(L)
Register Direct, Two Registers Figure 6. Direct Register Addressing, Two Registers
Rd and Rr
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Operands are contained in register r (Rr) and d (Rd). The result is stored in register d |
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(Rd). |
I/O Direct |
Figure 7. I/O Direct Addressing |
Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
Data Direct |
Figure 8. Direct Data Addressing |
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Data Space |
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31 |
20 19 |
16 |
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$0000 |
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OP |
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Rr/Rd |
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16 LSBs |
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15 |
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0 |
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$00DF
13
1477J–AVR–06/07
Data Indirect with Displacement
Data Indirect
Data Indirect with Predecrement
A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register.
Figure 9. Data Indirect with Displacement
Data Space
$0000
15 |
0 |
Y OR Z - REGISTER
15 |
10 |
6 |
5 |
0 |
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OP |
n |
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a |
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$00DF
Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction word.
Figure 10. Data Indirect Addressing
Data Space
$0000
15 |
0 |
X-, Y-, OR Z-REGISTER
$00DF
Operand address is the contents of the X-, Y-, or the Z-register.
Figure 11. Data Indirect Addressing with Pre-decrement
Data Space
$0000
15 |
0 |
X-, Y-, OR Z-REGISTER
-1
$00DF
14 ATtiny26(L)
1477J–AVR–06/07
Data Indirect with Postincrement
Constant Addressing Using
the LPM Instruction
1477J–AVR–06/07
ATtiny26(L)
The X-, Y-, or Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or Z-register.
Figure 12. Data Indirect Addressing with Post-increment
Data Space
$0000
15 |
0 |
X-, Y-, OR Z-REGISTER
1
$00DF
The X-, Y-, or Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or Z-register prior to incrementing.
Figure 13. Code Memory Constant Addressing
PROGRAM MEMORY
$000
$3FF
Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 1K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1).
15
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Indirect Program Addressing, |
Figure 14. Indirect Program Memory Addressing |
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IJMP and ICALL |
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PROGRAM MEMORY |
$000
$3FF
Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register).
Relative Program Addressing, Figure 15. Relative Program Memory Addressing
RJMP and RCALL
PROGRAM MEMORY
$000
+1
$3FF
Program execution continues at address PC + k + 1. The relative address k is from -2048 to 2047.
16 ATtiny26(L)
1477J–AVR–06/07