- •Features
- •Pin Configuration
- •Description
- •Block Diagram
- •Pin Descriptions
- •AVCC
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •XTAL1
- •XTAL2
- •Resources
- •AVR CPU Core
- •Architectural Overview
- •I/O Direct
- •Data Direct
- •Data Indirect with Displacement
- •Data Indirect
- •Memories
- •SRAM Data Memory
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected Pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Register Description for I/O Ports
- •Interrupts
- •Interrupt Vectors
- •Interrupt Handling
- •Interrupt Response Time
- •External Interrupt
- •Pin Change Interrupt
- •Timer/Counters
- •Timer/Counter0 Prescaler
- •Timer/Counter1 Prescaler
- •8-bit Timer/Counter0
- •8-bit Timer/Counter1
- •Timer/Counter1 in PWM Mode
- •Watchdog Timer
- •Overview
- •Register Descriptions
- •Functional Descriptions
- •Three-wire Mode
- •SPI Slave Operation Example
- •Two-wire Mode
- •Start Condition Detector
- •Alternative USI Usage
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •Changing Channel or Reference Selection
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •ADC Characteristics
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATtiny26 Rev. B/C/D
- •Table of Contents
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ATtiny26(L) |
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Latching of Fuses |
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The fuse values are latched when the device enters programming mode and changes of |
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the fuse values will have no effect until the part leaves programming mode. This does |
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not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses |
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are also latched on Power-up in normal mode. |
Signature Bytes
Calibration Byte
All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space.
For the ATtiny26 the signature bytes are:
1.$000: $1E (indicates manufactured by Atmel).
2.$001: $91 (indicates 2KB Flash memory).
3.$002: $09 (indicates ATtiny26 device when $001 is $91).
The ATtiny26 stores four different calibration values for the internal RC Oscillator. These bytes resides in the signature row high byte of the addresses 0x0000, 0x0001, 0x0002, and 0x0003 for 1, 2, 4, and 8 MHz respectively. During Reset, the 1 MHz value is automatically loaded into the OSCCAL Register. If other frequencies are used, the calibration value has to be loaded manually, see “Oscillator Calibration Register – OSCCAL” on page 30 for details.
Page Size
Parallel Programming
Parameters, Pin
Mapping, and
Commands
Signal Names
Table 52. No. of Words in a Page and no. of Pages in the Flash
Flash Size |
Page Size |
PCWORD |
No. of Pages |
PCPAGE |
PCMSB |
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1K words (2K bytes) |
16 words |
PC[3:0] |
64 |
PC[9:4] |
9 |
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Table 53. No. of Words in a Page and no. of Pages in the EEPROM
EEPROM Size |
Page Size |
PCWORD |
No. of Pages |
PCPAGE |
EEAMSB |
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128 bytes |
4 bytes |
EEA[1:0] |
32 |
EEA[7:0] |
7 |
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This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATtiny26. Pulses are assumed to be at least 250 ns unless otherwise noted.
In this section, some pins of the ATtiny26 are referenced by signal names describing their functionality during parallel programming, see Figure 58 and Table 54. Pins not described in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 56.
When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 57.
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Figure 58. Parallel Programming
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WR |
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+5V |
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PB0 |
VCC |
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XA0 |
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PB1 |
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+5V |
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XA1/BS2 |
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PB2 |
AVCC |
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PAGEL/BS1 |
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PB3 |
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DATA |
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PA7: PA0 |
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PB5 |
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OE |
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PB6 |
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RDY/BSY |
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+12 V RESET
XTAL1/PB4
GND
Table 54. Pin Name Mapping
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Signal Name in |
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Programming Mode |
Pin Name |
I/O |
Function |
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PB0 |
I |
Write Pulse (Active low) |
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XA0 |
PB1 |
I |
XTAL Action Bit 0 |
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XA1/BS2(1) |
PB2 |
I |
XTAL Action Bit 1 multiplexed with Byte Select 2 |
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(“0” selects low byte, “1” selects 2’nd high byte) |
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Program Memory and EEPROM data Page Load |
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PB3 |
I |
multiplexed with Byte Select 1 (“0” selects low |
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byte, “1” selects high byte). |
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PB5 |
I |
Output Enable (Active low) |
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0: Device is busy programming, 1: Device is ready |
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RDY/BSY |
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PB6 |
O |
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DATA |
PA7:0 |
I/O |
Bidirectional Data bus (Output when |
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OE |
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Note: 1. The pin is used for two different control signals. In the description below, normally only one of the signals is referred. E.g., “give BS1 a positive pulse” equals “give PAGEL/BS1 a positive pulse”.
Table 55. Pin Values used to Enter Programming Mode
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PAGEL/BS1 |
Prog_enable[3] |
0 |
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XA1/BS2 |
Prog_enable[2] |
0 |
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XA0 |
Prog_enable[1] |
0 |
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Prog_enable[0] |
0 |
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WR |
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112 ATtiny26(L)
1477J–AVR–06/07
ATtiny26(L)
Table 56. XA1 and XA0 Coding(1)
XA1 |
XA0 |
Action when XTAL1 is Pulsed |
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0 |
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Load Flash or EEPROM Address (High or low address byte determined by |
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0 |
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Load Data (High or Low data byte for Flash determined by BS1). |
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1 |
0 |
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Load Command |
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1 |
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No Action, Idle |
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Note: |
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[XA1, XA0] = 0b11 is “No Action, Idle”. As long as XTAL1 is not pulsed, the Com- |
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mand, Address, and Data Registers remain unchanged. Therefore, there are no |
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problems using BS2 as described below even though BS2 is multiplexed with XA1. |
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BS2 is only asserted when reading the fuses |
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is low) and XTAL1 is not pulsed. |
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(OE |
Table 57. Command Byte Bit Coding
Command Byte |
Command Executed |
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1000 0000 |
Chip Erase |
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0100 0000 |
Write Fuse Bits |
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0010 0000 |
Write Lock Bits |
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0001 0000 |
Write Flash |
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0001 0001 |
Write EEPROM |
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0000 1000 |
Read Signature Bytes and Calibration Byte |
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0000 0100 |
Read Fuse and Lock Bits |
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0000 0010 |
Read Flash |
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0000 0011 |
Read EEPROM |
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113
1477J–AVR–06/07