ATtiny26(L)

Analog Comparator The Analog Comparator compares the input values on the positive pin PA6 (AIN0) and negative pin PA7 (AIN1). When the voltage on the positive pin PA6 (AIN0) is higher than the voltage on the negative pin PA7 (AIN1), the Analog Comparator Output, ACO is set (one). The comparator’s output can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in the Figure 50.

Figure 50. Analog Comparator Block Diagram

ACBG

PA6

(AIN0)

MUX

PA7

(AIN1) MUX

ACME

ADC

MULTIPLEXER OUTPUT

Analog Comparator Control

and Status Register – ACSR

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Bit	7	6	5	4	3	2	1	0
$08 ($28)	ACD	ACBG	ACO	ACI	ACIE	ACME	ACIS1	ACIS0	ACSR
Read/Write	R/W	R/W	R	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	X	0	0	0	0	0

• Bit 7 – ACD: Analog Comparator Disable

When this bit is set(one), the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set (one), it selects internal bandgap reference voltage (1.18V) as the positive comparator input.

• Bit 5 – ACO: Analog Comparator Output

ACO is directly connected to the comparator output.

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• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Analog Comparator interrupt is activated. When cleared (zero), the interrupt is disabled.

• Bit 2 – ACME: Analog Comparator Multiplexer Enable

When the ACME bit is set (one) and the ADC is switched off (ADEN in ADCSR is zero), MUX3...0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in Table 42 on page 95. If ACME is cleared (zero) or ADEN is set (one), PA7(AIN1) is applied to the negative input to the Analog Comparator.

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 41.

Table 41.	ACIS1/ACIS0 Settings(1)
ACIS1		ACIS0	Interrupt Mode
0		0	Comparator Interrupt on Output Toggle
0		1	Reserved
1		0	Comparator Interrupt on Falling Output Edge
1		1	Comparator Interrupt on Rising Output Edge

Note: 1. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.

94 ATtiny26(L)

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							ATtiny26(L)
		Table 42. Analog Comparator Input Selection(1)
		ACME		ADEN	MUX3...0(3)	Analog Comparator Negative Input
		0		X	XXXX	AIN1
		1		1	XXXX	AIN1
		1		0	0000	ADC0
		1		0	0001	ADC1
		1		0	0010	ADC2
		1		0	0011	ADC3
		1		0	0100	ADC4
		1		0	0101	ADC5
		1		0	0110	ADC6(2)
		1		0	0111	ADC7(2)
		1		0	1000	ADC8
		1		0	1001	ADC9
		1		0	1010	ADC10
		1		0	1011	Undefined
		1		0	1100	Undefined
		1		0	1101	Undefined
		1		0	1110	Undefined
		1		0	1111	Undefined
		Notes: 1.	MUX4 does not affect Analog Comparator input selection.

2.Pin change interrupt on PA6 and PA7 is disabled if the Analog Comparator is enabled. This happens regardless of whether AIN1 or AIN0 has been replaced as inputs to the Analog Comparator.

3.The MUX3...0 selections go into effect after one clock cycle delay.

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